Lines Matching defs:clock
481 /* Change clock frequency for the first UART. */
1037 * Determine the oversampling rate, the clock prescaler, and the clock
1038 * divisor for the requested baud rate. The clock rate is 62.5 MHz,
1041 * to use a scaled clock rate, which is the baud base multiplied by 32
1042 * (or our assumed UART clock rate multiplied by 2).
1045 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows
1047 * 0.000 to 0.875 has not been specified). The clock divisor is the usual
1051 * oversampling rates and clock prescalers that records all possible
1059 * rate and a clock prescaler that gives the lowest integer division
1061 * looking for it right away. We do some fixup if the resulting clock
1065 * 4-bit value of the oversampling rate and the 9-bit value of the clock
1181 * Set the oversampling rate in the transmitter clock cycle register (TCR),
1182 * the clock prescaler in the clock prescaler register (CPR and CPR2), and
1183 * the clock divisor in the divisor latch (DLL and DLM). Note that for
1218 * We require EFR features for clock programming, so set UPF_FULL_PROBE
1377 unsigned long clock;
1387 clock = 1843200;
1393 clock = 1843200;
1398 clock = 3685400;
1401 clock = 7372800;
1404 clock = 14745600;
1407 clock = 1843200;
1415 return clock;