Lines Matching defs:uart
482 dev_warn(&pdev->dev, "Can't get uart clock\n");
514 struct uart_8250_port uart = {};
529 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
531 if (!uart.port.membase)
541 err = mtk8250_probe_of(pdev, &uart.port, data);
547 spin_lock_init(&uart.port.lock);
548 uart.port.mapbase = regs->start;
549 uart.port.irq = irq;
550 uart.port.pm = mtk8250_do_pm;
551 uart.port.type = PORT_16550;
552 uart.port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
553 uart.port.dev = &pdev->dev;
554 uart.port.iotype = UPIO_MEM32;
555 uart.port.regshift = 2;
556 uart.port.private_data = data;
557 uart.port.shutdown = mtk8250_shutdown;
558 uart.port.startup = mtk8250_startup;
559 uart.port.set_termios = mtk8250_set_termios;
560 uart.port.uartclk = clk_get_rate(data->uart_clk);
563 uart.dma = data->dma;
567 writel(0x0, uart.port.membase +
568 (MTK_UART_RATE_FIX << uart.port.regshift));
572 data->line = serial8250_register_8250_port(&uart);
643 { .compatible = "mediatek,mt6577-uart" },
650 .name = "mt6577-uart",
672 OF_EARLYCON_DECLARE(mtk8250, "mediatek,mt6577-uart", early_mtk8250_setup);