Lines Matching defs:uart
153 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart",
156 OF_EARLYCON_DECLARE(jz4750_uart, "ingenic,jz4750-uart",
159 OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart",
162 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart",
165 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart",
168 OF_EARLYCON_DECLARE(x1000_uart, "ingenic,x1000-uart",
233 struct uart_8250_port uart = {};
259 spin_lock_init(&uart.port.lock);
260 uart.port.type = PORT_16550A;
261 uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE;
262 uart.port.iotype = UPIO_MEM;
263 uart.port.mapbase = regs->start;
264 uart.port.regshift = 2;
265 uart.port.serial_out = ingenic_uart_serial_out;
266 uart.port.serial_in = ingenic_uart_serial_in;
267 uart.port.irq = irq;
268 uart.port.dev = &pdev->dev;
269 uart.port.fifosize = cdata->fifosize;
270 uart.tx_loadsz = cdata->tx_loadsz;
271 uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE;
276 uart.port.line = line;
278 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
280 if (!uart.port.membase)
304 uart.port.uartclk = clk_get_rate(data->clk_baud);
306 data->line = serial8250_register_8250_port(&uart);
354 { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config },
355 { .compatible = "ingenic,jz4750-uart", .data = &jz4760_uart_config },
356 { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config },
357 { .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config },
358 { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config },
359 { .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config },
360 { .compatible = "ingenic,x1000-uart", .data = &x1000_uart_config },
367 .name = "ingenic-uart",