Lines Matching refs:dma
10 #include <linux/dma-mapping.h>
17 struct uart_8250_dma *dma = p->dma;
22 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
27 dma->tx_running = 0;
29 uart_xmit_advance(&p->port, dma->tx_size);
35 if (ret || !dma->tx_running)
43 struct uart_8250_dma *dma = p->dma;
54 dma_status = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
58 count = dma->rx_size - state.residue;
60 tty_insert_flip_string(tty_port, dma->rx_buf, count);
62 dma->rx_running = 0;
70 struct uart_8250_dma *dma = p->dma;
74 if (dma->rx_running)
79 * changes dma->rx_running.
81 if (!dma->rx_running && (serial_lsr_in(p) & UART_LSR_DR))
82 p->dma->rx_dma(p);
88 struct uart_8250_dma *dma = p->dma;
94 if (dma->tx_running) {
96 dmaengine_pause(dma->txchan);
98 dmaengine_resume(dma->txchan);
110 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
114 desc = dmaengine_prep_slave_single(dma->txchan,
115 dma->tx_addr + xmit->tail,
116 dma->tx_size, DMA_MEM_TO_DEV,
123 dma->tx_running = 1;
127 dma->tx_cookie = dmaengine_submit(desc);
129 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
132 dma_async_issue_pending(dma->txchan);
134 dma->tx_err = 0;
138 dma->tx_err = 1;
144 struct uart_8250_dma *dma = p->dma;
147 if (dma->rx_running)
152 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
153 dma->rx_size, DMA_DEV_TO_MEM,
158 dma->rx_running = 1;
162 dma->rx_cookie = dmaengine_submit(desc);
164 dma_async_issue_pending(dma->rxchan);
171 struct uart_8250_dma *dma = p->dma;
173 if (dma->rx_running) {
174 dmaengine_pause(dma->rxchan);
176 dmaengine_terminate_async(dma->rxchan);
183 struct uart_8250_dma *dma = p->dma;
184 phys_addr_t rx_dma_addr = dma->rx_dma_addr ?
185 dma->rx_dma_addr : p->port.mapbase;
186 phys_addr_t tx_dma_addr = dma->tx_dma_addr ?
187 dma->tx_dma_addr : p->port.mapbase;
193 dma->rxconf.direction = DMA_DEV_TO_MEM;
194 dma->rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
195 dma->rxconf.src_addr = rx_dma_addr + UART_RX;
197 dma->txconf.direction = DMA_MEM_TO_DEV;
198 dma->txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
199 dma->txconf.dst_addr = tx_dma_addr + UART_TX;
205 dma->rxchan = dma_request_slave_channel_compat(mask,
206 dma->fn, dma->rx_param,
208 if (!dma->rxchan)
211 /* 8250 rx dma requires dmaengine driver to support pause/terminate */
212 ret = dma_get_slave_caps(dma->rxchan, &caps);
221 dmaengine_slave_config(dma->rxchan, &dma->rxconf);
224 dma->txchan = dma_request_slave_channel_compat(mask,
225 dma->fn, dma->tx_param,
227 if (!dma->txchan) {
232 /* 8250 tx dma requires dmaengine driver to support terminate */
233 ret = dma_get_slave_caps(dma->txchan, &caps);
241 dmaengine_slave_config(dma->txchan, &dma->txconf);
244 if (!dma->rx_size)
245 dma->rx_size = PAGE_SIZE;
247 dma->rx_buf = dma_alloc_coherent(dma->rxchan->device->dev, dma->rx_size,
248 &dma->rx_addr, GFP_KERNEL);
249 if (!dma->rx_buf) {
255 dma->tx_addr = dma_map_single(dma->txchan->device->dev,
259 if (dma_mapping_error(dma->txchan->device->dev, dma->tx_addr)) {
260 dma_free_coherent(dma->rxchan->device->dev, dma->rx_size,
261 dma->rx_buf, dma->rx_addr);
266 dev_dbg_ratelimited(p->port.dev, "got both dma channels\n");
270 dma_release_channel(dma->txchan);
272 dma_release_channel(dma->rxchan);
279 struct uart_8250_dma *dma = p->dma;
281 if (!dma)
285 dmaengine_terminate_sync(dma->rxchan);
286 dma_free_coherent(dma->rxchan->device->dev, dma->rx_size, dma->rx_buf,
287 dma->rx_addr);
288 dma_release_channel(dma->rxchan);
289 dma->rxchan = NULL;
292 dmaengine_terminate_sync(dma->txchan);
293 dma_unmap_single(dma->txchan->device->dev, dma->tx_addr,
295 dma_release_channel(dma->txchan);
296 dma->txchan = NULL;
297 dma->tx_running = 0;
299 dev_dbg_ratelimited(p->port.dev, "dma channels released\n");