Lines Matching defs:clear
383 * ignore it if MSI is clear ?
532 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
1033 unsigned int clear)
1046 if (clear & TIOCM_RTS)
1048 if (clear & TIOCM_DTR)
1208 * XXX It's not clear whether the current behavior is correct
1245 /* clear any pending receive interrupt */
1293 * ever clear. This assumes the UART isn't doing flow
1542 /* clear any pending interrupt */
1550 * and clear RTS and DTR