Lines Matching refs:ret
102 int ret;
104 ret = tb_nvm_validate(sw->nvm);
105 if (ret)
106 return ret;
108 ret = tb_nvm_write_headers(sw->nvm);
109 if (ret)
110 return ret;
116 ret = usb4_switch_nvm_write(sw, 0, buf, image_size);
118 ret = dma_port_flash_write(sw->dma_port, 0, buf, image_size);
119 if (ret)
120 return ret;
128 int ret = 0;
138 ret = tb_domain_disconnect_all_paths(sw->tb);
139 if (ret)
140 return ret;
145 ret = dma_port_flash_update_auth(sw->dma_port);
146 if (!ret || ret == -ETIMEDOUT)
163 return ret;
168 int ret, retries = 10;
170 ret = dma_port_flash_update_auth(sw->dma_port);
171 switch (ret) {
179 return ret;
191 ret = dma_port_flash_update_auth_status(sw->dma_port, &status);
192 if (ret < 0 && ret != -ETIMEDOUT)
193 return ret;
194 if (ret > 0) {
260 int ret;
264 ret = usb4_switch_nvm_set_offset(sw, 0);
265 if (ret)
266 return ret;
277 ret = nvm_authenticate_host_dma_port(sw);
279 ret = nvm_authenticate_device_dma_port(sw);
282 return ret;
308 int ret;
313 ret = restart_syscall();
317 ret = tb_switch_nvm_read(sw, offset, val, bytes);
324 return ret;
331 int ret;
342 ret = tb_nvm_write_buf(nvm, offset, val, bytes);
345 return ret;
351 int ret;
358 ret = PTR_ERR(nvm) == -EOPNOTSUPP ? 0 : PTR_ERR(nvm);
362 ret = tb_nvm_read_version(nvm);
363 if (ret)
372 ret = tb_nvm_add_active(nvm, nvm_read);
373 if (ret)
378 ret = tb_nvm_add_non_active(nvm, nvm_write);
379 if (ret)
392 return ret;
630 int ret;
636 ret = tb_port_read(port, &phy, TB_CFG_PORT,
638 if (ret)
639 return ret;
647 ret = tb_port_write(port, &phy, TB_CFG_PORT,
649 if (ret)
650 return ret;
894 int ret;
899 ret = tb_port_read(port, &val, TB_CFG_PORT,
901 if (ret)
902 return ret;
927 int ret;
932 ret = tb_port_read(port, &val, TB_CFG_PORT,
934 if (ret)
935 return ret;
946 int ret;
951 ret = tb_port_read(port, &phy, TB_CFG_PORT,
953 if (ret)
980 int ret;
985 ret = tb_port_read(port, &val, TB_CFG_PORT,
987 if (ret)
988 return ret;
1026 int ret;
1031 ret = tb_port_read(port, &val, TB_CFG_PORT,
1033 if (ret)
1034 return ret;
1060 int ret;
1068 ret = tb_port_set_link_width(port, TB_LINK_WIDTH_DUAL);
1069 if (ret)
1075 ret = tb_port_set_link_width(port->dual_link_port,
1077 if (ret)
1086 ret = tb_port_set_lane_bonding(port, true);
1087 if (ret)
1105 return ret;
1140 int ret;
1147 ret = tb_port_get_link_width(port);
1148 if (ret < 0) {
1154 if (ret != -EACCES)
1155 return ret;
1156 } else if (ret & width_mask) {
1169 int ret;
1171 ret = tb_port_read(port, &nfc_credits, TB_CFG_PORT, ADP_CS_4, 1);
1172 if (ret)
1173 return ret;
1201 int ret;
1203 ret = tb_port_do_update_credits(port);
1204 if (ret)
1205 return ret;
1211 int ret;
1216 ret = tb_lc_start_lane_initialization(port);
1217 return ret == -EINVAL ? 0 : ret;
1340 int ret;
1342 ret = tb_port_read(port, &data, TB_CFG_PORT,
1344 if (ret)
1345 return ret;
1359 int ret;
1361 ret = tb_port_read(port, &data, TB_CFG_PORT,
1363 if (ret)
1364 return ret;
1386 int ret;
1391 ret = tb_port_read(port, data, TB_CFG_PORT,
1393 if (ret)
1394 return ret;
1436 int ret;
1438 ret = tb_port_read(port, data, TB_CFG_PORT,
1440 if (ret)
1441 return ret;
1532 int ret;
1534 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1);
1535 if (ret)
1536 return ret;
1610 int ret;
1613 ret = device_for_each_child_reverse(&sw->dev, NULL, disapprove_switch);
1614 if (ret)
1615 return ret;
1617 ret = tb_domain_disapprove_switch(sw->tb, sw);
1618 if (ret)
1619 return ret;
1631 int ret = -EINVAL;
1644 ret = disapprove_switch(&sw->dev, NULL);
1652 ret = tb_domain_approve_switch_key(sw->tb, sw);
1654 ret = tb_domain_approve_switch(sw->tb, sw);
1660 ret = tb_domain_challenge_switch_key(sw->tb, sw);
1667 if (!ret) {
1679 return ret;
1688 ssize_t ret;
1690 ret = kstrtouint(buf, 0, &val);
1691 if (ret)
1692 return ret;
1697 ret = tb_switch_set_authorized(sw, val);
1701 return ret ? ret : count;
1745 ssize_t ret;
1751 ret = sysfs_emit(buf, "%*phN\n", TB_SWITCH_KEY_SIZE, sw->key);
1753 ret = sysfs_emit(buf, "\n");
1756 return ret;
1764 ssize_t ret = count;
1776 ret = -EBUSY;
1784 ret = -ENOMEM;
1789 return ret;
1874 int val, ret;
1879 ret = restart_syscall();
1884 ret = -EOPNOTSUPP;
1890 ret = -EAGAIN;
1894 ret = kstrtoint(buf, 10, &val);
1895 if (ret)
1904 ret = -EINVAL;
1906 ret = nvm_authenticate(sw, true);
1910 ret = -EINVAL;
1914 ret = nvm_validate_and_write(sw);
1915 if (ret || val == WRITE_ONLY)
1920 ret = tb_lc_force_power(sw);
1922 ret = nvm_authenticate(sw, false);
1933 return ret;
1939 int ret = nvm_authenticate_sysfs(dev, buf, false);
1940 if (ret)
1941 return ret;
1955 int ret;
1957 ret = nvm_authenticate_sysfs(dev, buf, true);
1958 return ret ? ret : count;
1966 int ret;
1972 ret = -ENODATA;
1974 ret = -EAGAIN;
1976 ret = sysfs_emit(buf, "%x.%x\n", sw->nvm->major, sw->nvm->minor);
1980 return ret;
2266 int i, ret, depth;
2288 ret = tb_cfg_read(tb->ctl, &sw->config, route, 0, TB_CFG_SWITCH, 0, 5);
2289 if (ret)
2306 ret = -EADDRNOTAVAIL;
2314 ret = -ENOMEM;
2330 ret = tb_switch_find_vse_cap(sw, TB_VSE_CAP_PLUG_EVENTS);
2331 if (ret > 0)
2332 sw->cap_plug_events = ret;
2334 ret = tb_switch_find_vse_cap(sw, TB_VSE_CAP_TIME2);
2335 if (ret > 0)
2336 sw->cap_vsec_tmu = ret;
2338 ret = tb_switch_find_vse_cap(sw, TB_VSE_CAP_LINK_CONTROLLER);
2339 if (ret > 0)
2340 sw->cap_lc = ret;
2342 ret = tb_switch_find_vse_cap(sw, TB_VSE_CAP_CP_LP);
2343 if (ret > 0)
2344 sw->cap_lp = ret;
2363 return ERR_PTR(ret);
2420 int ret;
2444 ret = tb_sw_write(sw, (u32 *)&sw->config + 1, TB_CFG_SWITCH,
2446 if (ret)
2447 return ret;
2449 ret = usb4_switch_setup(sw);
2461 ret = tb_sw_write(sw, (u32 *)&sw->config + 1, TB_CFG_SWITCH,
2464 if (ret)
2465 return ret;
2490 int ret;
2496 ret = usb4_switch_read_uid(sw, &sw->uid);
2497 if (ret)
2498 return ret;
2505 ret = tb_lc_read_uuid(sw, uuid);
2506 if (ret) {
2507 if (ret != -EINVAL)
2508 return ret;
2535 int ret;
2546 ret = tb_switch_set_uuid(sw);
2547 if (ret)
2548 return ret;
2565 ret = usb4_switch_nvm_authenticate_status(sw, &status);
2566 if (ret)
2567 return ret;
2603 ret = dma_port_flash_update_auth_status(sw->dma_port, &status);
2604 if (ret <= 0)
2605 return ret;
2672 int ret;
2679 ret = tb_port_get_link_speed(up);
2680 if (ret < 0)
2681 return ret;
2682 if (sw->link_speed != ret)
2684 sw->link_speed = ret;
2686 ret = tb_port_get_link_width(up);
2687 if (ret < 0)
2688 return ret;
2689 if (sw->link_width != ret)
2691 sw->link_width = ret;
2713 int ret;
2735 ret = tb_port_lane_bonding_enable(up);
2736 if (ret) {
2738 return ret;
2741 ret = tb_port_lane_bonding_enable(down);
2742 if (ret) {
2745 return ret;
2752 ret = tb_port_wait_for_link_width(down, width_mask, 100);
2753 if (ret) {
2755 return ret;
2763 return ret;
2776 int ret;
2794 ret = tb_port_wait_for_link_width(down, TB_LINK_WIDTH_SINGLE, 100);
2795 if (ret == -ETIMEDOUT)
2820 int ret;
2827 ret = usb4_port_configure(up);
2829 ret = tb_lc_configure_port(up);
2830 if (ret)
2831 return ret;
2912 int i, ret;
2921 ret = tb_switch_add_dma_port(sw);
2922 if (ret) {
2924 return ret;
2931 ret = tb_drom_read(sw);
2932 if (ret)
2933 dev_warn(&sw->dev, "reading DROM failed: %d\n", ret);
2936 ret = tb_switch_set_uuid(sw);
2937 if (ret) {
2939 return ret;
2947 ret = tb_init_port(&sw->ports[i]);
2948 if (ret) {
2950 return ret;
2958 ret = tb_switch_update_link_attributes(sw);
2959 if (ret)
2960 return ret;
2962 ret = tb_switch_clx_init(sw);
2963 if (ret)
2964 return ret;
2966 ret = tb_switch_tmu_init(sw);
2967 if (ret)
2968 return ret;
2971 ret = tb_switch_port_hotplug_enable(sw);
2972 if (ret)
2973 return ret;
2975 ret = device_add(&sw->dev);
2976 if (ret) {
2977 dev_err(&sw->dev, "failed to add device: %d\n", ret);
2978 return ret;
2989 ret = usb4_switch_add_ports(sw);
2990 if (ret) {
2995 ret = tb_switch_nvm_add(sw);
2996 if (ret) {
3025 return ret;
3273 int ret;
3276 ret = usb4_switch_alloc_dp_resource(sw, in);
3278 ret = tb_lc_dp_sink_alloc(sw, in);
3280 if (ret)
3286 return ret;
3299 int ret;
3302 ret = usb4_switch_dealloc_dp_resource(sw, in);
3304 ret = tb_lc_dp_sink_dealloc(sw, in);
3306 if (ret)
3449 int ret;
3455 ret = tb_sw_write(sw, &value, TB_CFG_SWITCH, offset, 1);
3456 if (ret)
3457 return ret;
3468 ret = tb_sw_write(sw, &command, TB_CFG_SWITCH, offset, 1);
3469 if (ret)
3470 return ret;
3472 ret = tb_switch_wait_for_bit(sw, offset,
3474 if (ret)
3475 return ret;
3477 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1);
3478 if (ret)
3479 return ret;
3499 int ret;
3512 ret = tb_switch_pcie_bridge_write(sw, 5, 0x143, 0x0c7806b1);
3513 if (ret)
3514 return ret;
3533 int ret;
3551 ret = tb_lc_xhci_connect(port1);
3552 if (ret)
3553 return ret;
3558 ret = tb_lc_xhci_connect(port1);
3559 if (ret)
3560 return ret;