Lines Matching defs:value
101 u32 value;
107 value = readl_relaxed(sensor->base + DTS_ITENR_OFFSET);
108 value &= ~(LOW_THRESHOLD | HIGH_THRESHOLD);
111 value |= HIGH_THRESHOLD;
114 value |= LOW_THRESHOLD;
117 writel_relaxed(value, sensor->base + DTS_ITENR_OFFSET);
142 u32 value;
145 value = readl_relaxed(sensor->base + DTS_CFGR1_OFFSET);
146 value |= TS1_EN;
147 writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
155 value, (value & TS_RDY),
161 value = readl_relaxed(sensor->base +
163 value |= TS1_START;
164 writel_relaxed(value, sensor->base +
174 u32 value;
179 value = readl_relaxed(sensor->base + DTS_CFGR1_OFFSET);
180 value &= ~TS1_START;
181 writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
187 value = readl_relaxed(sensor->base + DTS_CFGR1_OFFSET);
188 value &= ~TS1_EN;
189 writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
192 return readl_poll_timeout(sensor->base + DTS_SR_OFFSET, value,
193 !(value & TS_RDY),
199 u32 value, clk_freq;
202 /* Figure out prescaler value for PCLK during calibration */
214 value = readl_relaxed(sensor->base + DTS_CFGR1_OFFSET);
217 value &= ~HSREF_CLK_DIV_MASK;
220 value |= (prescaler << HSREF_CLK_DIV_POS);
223 value &= ~REFCLK_SEL;
226 value |= TS1_SMP_TIME_MASK;
229 value &= ~CALIBRATION_CONTROL;
232 value &= ~TS1_INTRIG_SEL_MASK;
233 value |= NO_HW_TRIG;
235 writel_relaxed(value, sensor->base + DTS_CFGR1_OFFSET);
292 u32 value;
295 value = readl_relaxed(sensor->base + DTS_ITENR_OFFSET);
296 value &= ~ITENR_MASK;
297 writel_relaxed(value, sensor->base + DTS_ITENR_OFFSET);