Lines Matching refs:reg

85 	/* Formula coeficients: temp = (b - m * reg) / div */
140 	u32 reg;
142 	regmap_read(priv->syscon, data->syscon_control1_off, &reg);
143 	reg |= PMU_TDC0_OTF_CAL_MASK;
146 	reg &= ~PMU_TDC0_REF_CAL_CNT_MASK;
147 	reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS);
150 	reg |= PMU_TDC0_SW_RST_MASK;
152 	regmap_write(priv->syscon, data->syscon_control1_off, reg);
154 	reg &= ~PMU_TDC0_SW_RST_MASK;
155 	regmap_write(priv->syscon, data->syscon_control1_off, reg);
158 	regmap_read(priv->syscon, data->syscon_status_off, &reg);
159 	reg &= ~PMU_TM_DISABLE_MASK;
160 	regmap_write(priv->syscon, data->syscon_status_off, reg);
167 	u32 reg;
169 	regmap_read(priv->syscon, data->syscon_control1_off, &reg);
170 	reg |= PMU_TDC0_OTF_CAL_MASK;
173 	reg &= ~PMU_TDC0_REF_CAL_CNT_MASK;
174 	reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS);
177 	reg &= ~PMU_TDC0_START_CAL_MASK;
179 	regmap_write(priv->syscon, data->syscon_control1_off, reg);
188 	u32 reg;
190 	regmap_read(priv->syscon, data->syscon_control1_off, &reg);
191 	reg &= ~(A375_UNIT_CONTROL_MASK << A375_UNIT_CONTROL_SHIFT);
192 	reg &= ~A375_READOUT_INVERT;
193 	reg &= ~A375_HW_RESETn;
194 	regmap_write(priv->syscon, data->syscon_control1_off, reg);
198 	reg |= A375_HW_RESETn;
199 	regmap_write(priv->syscon, data->syscon_control1_off, reg);
206 	u32 reg;
209 					priv->data->syscon_status_off, reg,
210 					reg & priv->data->is_valid_bit,
219 	u32 reg;
222 	regmap_read(priv->syscon, data->syscon_control1_off, &reg);
223 	reg |= CONTROL1_EXT_TSEN_HW_RESETn;
224 	reg &= ~CONTROL1_EXT_TSEN_SW_RESET;
225 	regmap_write(priv->syscon, data->syscon_control1_off, reg);
228 	regmap_read(priv->syscon, data->syscon_control0_off, &reg);
229 	reg &= ~CONTROL0_TSEN_TC_TRIM_MASK;
230 	reg |= CONTROL0_TSEN_TC_TRIM_VAL;
231 	regmap_write(priv->syscon, data->syscon_control0_off, reg);
238 	u32 reg;
240 	regmap_read(priv->syscon, data->syscon_control0_off, &reg);
241 	reg &= ~CONTROL0_TSEN_RESET;
242 	reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_ENABLE;
245 	reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT;
248 	reg &= ~CONTROL0_TSEN_AVG_BYPASS;
250 	regmap_write(priv->syscon, data->syscon_control0_off, reg);
257 	u32 reg;
262 	regmap_read(priv->syscon, data->syscon_control0_off, &reg);
263 	reg |= CONTROL0_TSEN_OSR_MAX << CONTROL0_TSEN_OSR_SHIFT;
264 	regmap_write(priv->syscon, data->syscon_control0_off, reg);
267 	regmap_read(priv->syscon, data->syscon_control1_off, &reg);
268 	reg &= ~CONTROL1_TSEN_AVG_MASK;
269 	reg |= 1;
270 	regmap_write(priv->syscon, data->syscon_control1_off, reg);
275 	u32 reg;
280 	regmap_read(priv->syscon, priv->data->syscon_status_off, &reg);
282 	return reg & priv->data->is_valid_bit;
288 	u32 reg;
291 	regmap_read(priv->syscon, data->dfx_irq_cause_off, &reg);
294 	regmap_read(priv->syscon, data->dfx_irq_mask_off, &reg);
295 	reg |= data->dfx_overheat_irq;
296 	regmap_write(priv->syscon, data->dfx_irq_mask_off, reg);
299 	regmap_read(priv->syscon, data->dfx_server_irq_mask_off, &reg);
300 	reg |= data->dfx_server_irq_en;
301 	regmap_write(priv->syscon, data->dfx_server_irq_mask_off, reg);
304 	regmap_read(priv->syscon, data->syscon_control1_off, &reg);
305 	reg |= CONTROL1_TSEN_INT_EN;
306 	regmap_write(priv->syscon, data->syscon_control1_off, reg);
313 	u32 reg;
315 	regmap_read(priv->syscon, data->syscon_control1_off, &reg);
316 	reg &= ~CONTROL1_TSEN_INT_EN;
317 	regmap_write(priv->syscon, data->syscon_control1_off, reg);
371 	u32 reg, div;
374 	regmap_read(priv->syscon, priv->data->syscon_status_off, &reg);
375 	reg = (reg >> priv->data->temp_shift) & priv->data->temp_mask;
378 		sample = sign_extend32(reg, fls(priv->data->temp_mask) - 1);
380 		sample = reg;