Lines Matching defs:pmic_arb
205 int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
207 int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
212 void __iomem *(*owner_acc_status)(struct spmi_pmic_arb *pmic_arb, u8 m,
214 void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n);
215 void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
216 void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
218 void __iomem *(*apid_owner)(struct spmi_pmic_arb *pmic_arb, u16 n);
221 static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,
224 writel_relaxed(val, pmic_arb->wr_base + offset);
227 static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb,
230 writel_relaxed(val, pmic_arb->rd_base + offset);
240 pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc)
242 u32 data = __raw_readl(pmic_arb->rd_base + reg);
253 static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf,
259 __raw_writel(data, pmic_arb->wr_base + reg);
266 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
272 rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type);
315 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
321 rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW);
328 raw_spin_lock_irqsave(&pmic_arb->lock, flags);
329 pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
330 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0,
332 raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
346 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
354 return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid);
357 static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc, u8 sid,
363 rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
370 dev_err(&pmic_arb->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
385 *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
394 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
398 pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd);
399 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr,
404 pmic_arb_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0,
408 pmic_arb_read_data(pmic_arb, buf + 4, offset + PMIC_ARB_RDATA1,
416 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
421 rc = pmic_arb_fmt_read_cmd(pmic_arb, opc, sid, addr, len, &cmd,
426 raw_spin_lock_irqsave(&pmic_arb->lock, flags);
428 raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
433 static int pmic_arb_fmt_write_cmd(struct spmi_pmic_arb *pmic_arb, u8 opc,
440 rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
447 dev_err(&pmic_arb->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
464 *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
473 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
477 pmic_arb_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0,
480 pmic_arb_write_data(pmic_arb, buf + 4, offset + PMIC_ARB_WDATA1,
484 pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
485 return pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr,
492 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
497 rc = pmic_arb_fmt_write_cmd(pmic_arb, opc, sid, addr, len, &cmd,
502 raw_spin_lock_irqsave(&pmic_arb->lock, flags);
505 raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
513 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
519 rc = pmic_arb_fmt_read_cmd(pmic_arb, SPMI_CMD_EXT_READL, sid, addr, len,
524 rc = pmic_arb_fmt_write_cmd(pmic_arb, SPMI_CMD_EXT_WRITEL, sid, addr,
529 raw_spin_lock_irqsave(&pmic_arb->lock, flags);
541 raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
567 struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
571 if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
573 dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
579 struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
583 if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, sid,
585 dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
593 struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
598 rc = pmic_arb_masked_write(pmic_arb->spmic, sid, (per << 8) + reg, buf,
601 dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x rc=%d\n",
606 static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id)
608 u16 ppid = pmic_arb->apid_data[apid].ppid;
613 dev_err_ratelimited(&pmic_arb->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n",
615 writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
618 static int periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid)
623 u8 sid = (pmic_arb->apid_data[apid].ppid >> 8) & 0xF;
624 u8 per = pmic_arb->apid_data[apid].ppid & 0xFF;
626 status = readl_relaxed(pmic_arb->ver_ops->irq_status(pmic_arb, apid));
630 irq = irq_find_mapping(pmic_arb->domain,
633 cleanup_irq(pmic_arb, apid, id);
645 struct spmi_pmic_arb *pmic_arb = irq_desc_get_handler_data(desc);
646 const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
648 int first = pmic_arb->min_apid;
649 int last = pmic_arb->max_apid;
654 int acc_offset = pmic_arb->base_apid >> 5;
655 u8 ee = pmic_arb->ee;
665 status = readl_relaxed(ver_ops->owner_acc_status(pmic_arb, ee, i - acc_offset));
679 ver_ops->acc_enable(pmic_arb, apid));
681 if (periph_interrupt(pmic_arb, apid) != 0)
690 if (pmic_arb->apid_data[i].irq_ee != pmic_arb->ee)
694 ver_ops->irq_status(pmic_arb, i));
697 ver_ops->acc_enable(pmic_arb, i));
699 dev_dbg(&pmic_arb->spmic->dev,
702 if (periph_interrupt(pmic_arb, i) != 0)
717 struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
722 writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
738 struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
739 const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
745 ver_ops->acc_enable(pmic_arb, apid));
802 struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
804 return irq_set_irq_wake(pmic_arb->irq, on);
826 struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
833 if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) {
834 dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",
835 sid, periph, irq, pmic_arb->ee,
836 pmic_arb->apid_data[apid].irq_ee);
848 .name = "pmic_arb",
863 struct spmi_pmic_arb *pmic_arb = d->host_data;
868 dev_dbg(&pmic_arb->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
871 if (irq_domain_get_of_node(d) != pmic_arb->spmic->dev.of_node)
879 rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
881 dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n",
888 if (apid > pmic_arb->max_apid)
889 pmic_arb->max_apid = apid;
890 if (apid < pmic_arb->min_apid)
891 pmic_arb->min_apid = apid;
896 dev_dbg(&pmic_arb->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
903 static void qpnpint_irq_domain_map(struct spmi_pmic_arb *pmic_arb,
909 dev_dbg(&pmic_arb->spmic->dev, "virq = %u, hwirq = %lu, type = %u\n",
920 irq_domain_set_info(domain, virq, hwirq, &pmic_arb_irqchip, pmic_arb,
928 struct spmi_pmic_arb *pmic_arb = domain->host_data;
939 qpnpint_irq_domain_map(pmic_arb, domain, virq + i, hwirq + i,
945 static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
947 u32 *mapping_table = pmic_arb->mapping_table;
953 apid_valid = pmic_arb->ppid_to_apid[ppid];
960 if (!test_and_set_bit(index, pmic_arb->mapping_table_valid))
961 mapping_table[index] = readl_relaxed(pmic_arb->cnfg +
971 pmic_arb->ppid_to_apid[ppid]
973 pmic_arb->apid_data[apid].ppid = ppid;
981 pmic_arb->ppid_to_apid[ppid]
983 pmic_arb->apid_data[apid].ppid = ppid;
993 static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
996 return 0x800 + 0x80 * pmic_arb->channel;
999 static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
1001 struct apid_data *apidd = &pmic_arb->apid_data[pmic_arb->last_apid];
1005 for (apid = pmic_arb->last_apid; ; apid++, apidd++) {
1006 offset = pmic_arb->ver_ops->apid_map_offset(apid);
1007 if (offset >= pmic_arb->core_size)
1010 regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(pmic_arb,
1015 regval = readl_relaxed(pmic_arb->core + offset);
1020 pmic_arb->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID;
1027 pmic_arb->last_apid = apid & ~PMIC_ARB_APID_VALID;
1032 static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
1036 apid_valid = pmic_arb->ppid_to_apid[ppid];
1038 apid_valid = pmic_arb_find_apid(pmic_arb, ppid);
1045 static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
1068 apidd = &pmic_arb->apid_data[pmic_arb->base_apid];
1069 apid_max = pmic_arb->base_apid + pmic_arb->apid_count;
1070 for (i = pmic_arb->base_apid; i < apid_max; i++, apidd++) {
1071 offset = pmic_arb->ver_ops->apid_map_offset(i);
1072 if (offset >= pmic_arb->core_size)
1075 regval = readl_relaxed(pmic_arb->core + offset);
1081 regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(pmic_arb,
1087 valid = pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID;
1088 apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
1089 prev_apidd = &pmic_arb->apid_data[apid];
1091 if (!valid || apidd->write_ee == pmic_arb->ee) {
1093 pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
1095 prev_apidd->write_ee == pmic_arb->ee) {
1104 pmic_arb->last_apid = i;
1108 dev_dbg(&pmic_arb->spmic->dev, "PPID APID Write-EE IRQ-EE\n");
1110 apid = pmic_arb->ppid_to_apid[ppid];
1113 apidd = &pmic_arb->apid_data[apid];
1114 dev_dbg(&pmic_arb->spmic->dev, "%#03X %3u %2u %2u\n",
1122 static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pmic_arb, u16 ppid)
1124 if (!(pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
1127 return pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
1131 static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
1139 rc = pmic_arb_ppid_to_apid_v2(pmic_arb, ppid);
1144 return 0x1000 * pmic_arb->ee + 0x8000 * apid;
1151 static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
1159 rc = pmic_arb_ppid_to_apid_v5(pmic_arb, ppid);
1166 offset = 0x10000 * pmic_arb->ee + 0x80 * apid;
1169 if (pmic_arb->apid_data[apid].write_ee != pmic_arb->ee) {
1170 dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",
1185 static int pmic_arb_offset_v7(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
1193 rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
1200 offset = 0x8000 * pmic_arb->ee + 0x20 * apid;
1203 if (pmic_arb->apid_data[apid].write_ee != pmic_arb->ee) {
1204 dev_err(&pmic_arb->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n",
1226 pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1228 return pmic_arb->intr + 0x20 * m + 0x4 * n;
1232 pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1234 return pmic_arb->intr + 0x100000 + 0x1000 * m + 0x4 * n;
1238 pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1240 return pmic_arb->intr + 0x200000 + 0x1000 * m + 0x4 * n;
1244 pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1246 return pmic_arb->intr + 0x10000 * m + 0x4 * n;
1250 pmic_arb_owner_acc_status_v7(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1252 return pmic_arb->intr + 0x1000 * m + 0x4 * n;
1256 pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1258 return pmic_arb->intr + 0x200 + 0x4 * n;
1262 pmic_arb_acc_enable_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1264 return pmic_arb->intr + 0x1000 * n;
1268 pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1270 return pmic_arb->wr_base + 0x100 + 0x10000 * n;
1274 pmic_arb_acc_enable_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
1276 return pmic_arb->wr_base + 0x100 + 0x1000 * n;
1280 pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1282 return pmic_arb->intr + 0x600 + 0x4 * n;
1286 pmic_arb_irq_status_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1288 return pmic_arb->intr + 0x4 + 0x1000 * n;
1292 pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1294 return pmic_arb->wr_base + 0x104 + 0x10000 * n;
1298 pmic_arb_irq_status_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
1300 return pmic_arb->wr_base + 0x104 + 0x1000 * n;
1304 pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1306 return pmic_arb->intr + 0xA00 + 0x4 * n;
1310 pmic_arb_irq_clear_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1312 return pmic_arb->intr + 0x8 + 0x1000 * n;
1316 pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1318 return pmic_arb->wr_base + 0x108 + 0x10000 * n;
1322 pmic_arb_irq_clear_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
1324 return pmic_arb->wr_base + 0x108 + 0x1000 * n;
1343 pmic_arb_apid_owner_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1345 return pmic_arb->cnfg + 0x700 + 0x4 * n;
1354 pmic_arb_apid_owner_v7(struct spmi_pmic_arb *pmic_arb, u16 n)
1356 return pmic_arb->cnfg + 0x4 * (n - pmic_arb->base_apid);
1438 struct spmi_pmic_arb *pmic_arb;
1446 ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pmic_arb));
1450 pmic_arb = spmi_controller_get_drvdata(ctrl);
1451 pmic_arb->spmic = ctrl;
1470 pmic_arb->core_size = resource_size(res);
1472 pmic_arb->ppid_to_apid = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PPID,
1473 sizeof(*pmic_arb->ppid_to_apid),
1475 if (!pmic_arb->ppid_to_apid) {
1483 pmic_arb->ver_ops = &pmic_arb_v1;
1484 pmic_arb->wr_base = core;
1485 pmic_arb->rd_base = core;
1487 pmic_arb->core = core;
1490 pmic_arb->ver_ops = &pmic_arb_v2;
1492 pmic_arb->ver_ops = &pmic_arb_v3;
1494 pmic_arb->ver_ops = &pmic_arb_v5;
1496 pmic_arb->ver_ops = &pmic_arb_v7;
1500 pmic_arb->rd_base = devm_ioremap(&ctrl->dev, res->start,
1502 if (IS_ERR(pmic_arb->rd_base)) {
1503 err = PTR_ERR(pmic_arb->rd_base);
1509 pmic_arb->wr_base = devm_ioremap(&ctrl->dev, res->start,
1511 if (IS_ERR(pmic_arb->wr_base)) {
1512 err = PTR_ERR(pmic_arb->wr_base);
1517 pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS;
1520 pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS_V7;
1523 &pmic_arb->bus_instance);
1524 if (pmic_arb->bus_instance > 1) {
1527 pmic_arb->bus_instance);
1531 if (pmic_arb->bus_instance == 0) {
1532 pmic_arb->base_apid = 0;
1533 pmic_arb->apid_count =
1537 pmic_arb->base_apid =
1540 pmic_arb->apid_count =
1545 if (pmic_arb->base_apid + pmic_arb->apid_count > pmic_arb->max_periphs) {
1548 pmic_arb->base_apid + pmic_arb->apid_count);
1552 pmic_arb->base_apid = 0;
1553 pmic_arb->apid_count = readl_relaxed(core + PMIC_ARB_FEATURES) &
1556 if (pmic_arb->apid_count > pmic_arb->max_periphs) {
1559 pmic_arb->apid_count);
1564 pmic_arb->apid_data = devm_kcalloc(&ctrl->dev, pmic_arb->max_periphs,
1565 sizeof(*pmic_arb->apid_data),
1567 if (!pmic_arb->apid_data) {
1573 pmic_arb->ver_ops->ver_str, hw_ver);
1576 pmic_arb->intr = devm_ioremap_resource(&ctrl->dev, res);
1577 if (IS_ERR(pmic_arb->intr)) {
1578 err = PTR_ERR(pmic_arb->intr);
1583 pmic_arb->cnfg = devm_ioremap_resource(&ctrl->dev, res);
1584 if (IS_ERR(pmic_arb->cnfg)) {
1585 err = PTR_ERR(pmic_arb->cnfg);
1589 pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq");
1590 if (pmic_arb->irq < 0) {
1591 err = pmic_arb->irq;
1608 pmic_arb->channel = channel;
1622 pmic_arb->ee = ee;
1623 mapping_table = devm_kcalloc(&ctrl->dev, pmic_arb->max_periphs,
1630 pmic_arb->mapping_table = mapping_table;
1633 pmic_arb->max_apid = 0;
1634 pmic_arb->min_apid = pmic_arb->max_periphs - 1;
1637 raw_spin_lock_init(&pmic_arb->lock);
1644 err = pmic_arb_read_apid_map_v5(pmic_arb);
1653 pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node,
1654 &pmic_arb_irq_domain_ops, pmic_arb);
1655 if (!pmic_arb->domain) {
1661 irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq,
1662 pmic_arb);
1670 irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
1671 irq_domain_remove(pmic_arb->domain);
1680 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
1682 irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
1683 irq_domain_remove(pmic_arb->domain);