Lines Matching defs:sspi
117 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
119 return readl(sspi->base_addr + reg);
122 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
124 writel(value, sspi->base_addr + reg);
127 static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi)
129 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
134 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
136 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
141 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
143 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
146 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
149 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi)
155 len = sun6i_spi_get_rx_fifo_count(sspi);
158 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
159 if (sspi->rx_buf)
160 *sspi->rx_buf++ = byte;
164 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi)
171 cnt = sspi->cfg->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
173 len = min((int)cnt, sspi->len);
176 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
177 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
178 sspi->len--;
184 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
187 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
196 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
206 struct sun6i_spi *sspi = param;
208 complete(&sspi->dma_rx_done);
211 static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi,
215 struct spi_master *master = sspi->master;
221 .src_addr = sspi->dma_addr_rx,
235 rxdesc->callback_param = sspi;
243 .dst_addr = sspi->dma_addr_tx,
279 struct sun6i_spi *sspi = spi_master_get_devdata(master);
291 reinit_completion(&sspi->done);
292 reinit_completion(&sspi->dma_rx_done);
293 sspi->tx_buf = tfr->tx_buf;
294 sspi->rx_buf = tfr->rx_buf;
295 sspi->len = tfr->len;
299 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
302 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
314 trig_level = sspi->cfg->fifo_depth / 4 * 3;
321 trig_level = sspi->cfg->fifo_depth / 2;
332 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg);
338 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
359 if (sspi->rx_buf) {
369 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
371 if (sspi->cfg->has_clk_ctl) {
372 unsigned int mclk_rate = clk_get_rate(sspi->mclk);
376 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
377 mclk_rate = clk_get_rate(sspi->mclk);
405 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
407 clk_set_rate(sspi->mclk, tfr->speed_hz);
408 tfr->effective_speed_hz = clk_get_rate(sspi->mclk);
419 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
427 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
431 reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
433 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
436 if (sspi->tx_buf) {
456 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, reg);
457 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
458 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
462 sun6i_spi_fill_fifo(sspi);
464 ret = sun6i_spi_prepare_dma(sspi, tfr);
477 if (rx_len > sspi->cfg->fifo_depth)
479 if (tx_len > sspi->cfg->fifo_depth)
483 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
486 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
487 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
491 timeout = wait_for_completion_timeout(&sspi->done,
495 sun6i_spi_drain_fifo(sspi);
502 timeout = wait_for_completion_timeout(&sspi->dma_rx_done,
518 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
530 struct sun6i_spi *sspi = dev_id;
531 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
535 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
536 complete(&sspi->done);
542 sun6i_spi_drain_fifo(sspi);
544 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
550 sun6i_spi_fill_fifo(sspi);
552 if (!sspi->len)
554 sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
557 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
568 struct sun6i_spi *sspi = spi_master_get_devdata(master);
571 ret = clk_prepare_enable(sspi->hclk);
577 ret = clk_prepare_enable(sspi->mclk);
583 ret = reset_control_deassert(sspi->rstc);
589 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
595 clk_disable_unprepare(sspi->mclk);
597 clk_disable_unprepare(sspi->hclk);
605 struct sun6i_spi *sspi = spi_master_get_devdata(master);
607 reset_control_assert(sspi->rstc);
608 clk_disable_unprepare(sspi->mclk);
609 clk_disable_unprepare(sspi->hclk);
618 struct sun6i_spi *sspi = spi_master_get_devdata(master);
625 return xfer->len > sspi->cfg->fifo_depth;
631 struct sun6i_spi *sspi;
642 sspi = spi_master_get_devdata(master);
644 sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
645 if (IS_ERR(sspi->base_addr)) {
646 ret = PTR_ERR(sspi->base_addr);
657 0, "sun6i-spi", sspi);
663 sspi->master = master;
664 sspi->cfg = of_device_get_match_data(&pdev->dev);
673 sspi->cfg->mode_bits;
679 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
680 if (IS_ERR(sspi->hclk)) {
682 ret = PTR_ERR(sspi->hclk);
686 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
687 if (IS_ERR(sspi->mclk)) {
689 ret = PTR_ERR(sspi->mclk);
693 init_completion(&sspi->done);
694 init_completion(&sspi->dma_rx_done);
696 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
697 if (IS_ERR(sspi->rstc)) {
699 ret = PTR_ERR(sspi->rstc);
725 sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG;
726 sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG;