Lines Matching defs:sspi
90 static inline u32 sun4i_spi_read(struct sun4i_spi *sspi, u32 reg)
92 return readl(sspi->base_addr + reg);
95 static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
97 writel(value, sspi->base_addr + reg);
100 static inline u32 sun4i_spi_get_tx_fifo_count(struct sun4i_spi *sspi)
102 u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
109 static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32 mask)
111 u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
114 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
117 static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32 mask)
119 u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
122 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
125 static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
131 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
139 byte = readb(sspi->base_addr + SUN4I_RXDATA_REG);
140 if (sspi->rx_buf)
141 *sspi->rx_buf++ = byte;
145 static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
151 cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi);
153 len = min3(len, (int)cnt, sspi->len);
156 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
157 writeb(byte, sspi->base_addr + SUN4I_TXDATA_REG);
158 sspi->len--;
164 struct sun4i_spi *sspi = spi_master_get_devdata(spi->master);
167 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
196 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
208 struct sun4i_spi *sspi = spi_master_get_devdata(master);
222 reinit_completion(&sspi->done);
223 sspi->tx_buf = tfr->tx_buf;
224 sspi->rx_buf = tfr->rx_buf;
225 sspi->len = tfr->len;
228 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, ~0);
231 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
234 sun4i_spi_write(sspi, SUN4I_CTL_REG,
261 if (sspi->rx_buf)
266 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
269 mclk_rate = clk_get_rate(sspi->mclk);
271 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
272 mclk_rate = clk_get_rate(sspi->mclk);
300 sun4i_spi_write(sspi, SUN4I_CLK_CTL_REG, reg);
303 if (sspi->tx_buf)
307 sun4i_spi_write(sspi, SUN4I_BURST_CNT_REG, SUN4I_BURST_CNT(tfr->len));
308 sun4i_spi_write(sspi, SUN4I_XMIT_CNT_REG, SUN4I_XMIT_CNT(tx_len));
315 sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
318 sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TC |
322 sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
325 reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
326 sun4i_spi_write(sspi, SUN4I_CTL_REG, reg | SUN4I_CTL_XCH);
330 timeout = wait_for_completion_timeout(&sspi->done,
344 sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
351 struct sun4i_spi *sspi = dev_id;
352 u32 status = sun4i_spi_read(sspi, SUN4I_INT_STA_REG);
356 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
357 sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
358 complete(&sspi->done);
364 sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
366 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_RF_F34);
372 sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
374 if (!sspi->len)
376 sun4i_spi_disable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
379 sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TF_E34);
390 struct sun4i_spi *sspi = spi_master_get_devdata(master);
393 ret = clk_prepare_enable(sspi->hclk);
399 ret = clk_prepare_enable(sspi->mclk);
405 sun4i_spi_write(sspi, SUN4I_CTL_REG,
411 clk_disable_unprepare(sspi->hclk);
419 struct sun4i_spi *sspi = spi_master_get_devdata(master);
421 clk_disable_unprepare(sspi->mclk);
422 clk_disable_unprepare(sspi->hclk);
430 struct sun4i_spi *sspi;
440 sspi = spi_master_get_devdata(master);
442 sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
443 if (IS_ERR(sspi->base_addr)) {
444 ret = PTR_ERR(sspi->base_addr);
455 0, "sun4i-spi", sspi);
461 sspi->master = master;
473 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
474 if (IS_ERR(sspi->hclk)) {
476 ret = PTR_ERR(sspi->hclk);
480 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
481 if (IS_ERR(sspi->mclk)) {
483 ret = PTR_ERR(sspi->mclk);
487 init_completion(&sspi->done);