Lines Matching refs:spi
20 #include <linux/spi/spi.h>
246 int (*get_fifo_size)(struct stm32_spi *spi);
247 int (*get_bpw_mask)(struct stm32_spi *spi);
248 void (*disable)(struct stm32_spi *spi);
249 int (*config)(struct stm32_spi *spi);
250 void (*set_bpw)(struct stm32_spi *spi);
251 int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type);
252 void (*set_data_idleness)(struct stm32_spi *spi, u32 length);
253 int (*set_number_of_data)(struct stm32_spi *spi, u32 length);
254 void (*transfer_one_dma_start)(struct stm32_spi *spi);
257 int (*transfer_one_irq)(struct stm32_spi *spi);
362 static inline void stm32_spi_set_bits(struct stm32_spi *spi,
365 writel_relaxed(readl_relaxed(spi->base + offset) | bits,
366 spi->base + offset);
369 static inline void stm32_spi_clr_bits(struct stm32_spi *spi,
372 writel_relaxed(readl_relaxed(spi->base + offset) & ~bits,
373 spi->base + offset);
378 * @spi: pointer to the spi controller data structure
380 static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi)
385 spin_lock_irqsave(&spi->lock, flags);
387 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
389 while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP)
390 writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR);
392 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
394 spin_unlock_irqrestore(&spi->lock, flags);
396 dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count);
403 * @spi: pointer to the spi controller data structure
405 static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi)
407 dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n");
413 * @spi: pointer to the spi controller data structure
415 static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
420 spin_lock_irqsave(&spi->lock, flags);
426 stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
428 cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
431 spin_unlock_irqrestore(&spi->lock, flags);
433 dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw);
440 * @spi: pointer to the spi controller data structure
447 static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz,
452 /* Ensure spi->clk_rate is even */
453 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz);
471 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
473 spi->cur_half_period = DIV_ROUND_CLOSEST(USEC_PER_SEC, 2 * spi->cur_speed);
480 * @spi: pointer to the spi controller data structure
483 static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
488 packet = clamp(xfer_len, 1U, spi->fifo_size / 2);
491 bpw = DIV_ROUND_UP(spi->cur_bpw, 8);
497 * @spi: pointer to the spi controller data structure
502 static void stm32f4_spi_write_tx(struct stm32_spi *spi)
504 if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
506 u32 offs = spi->cur_xferlen - spi->tx_len;
508 if (spi->cur_bpw == 16) {
509 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
511 writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR);
512 spi->tx_len -= sizeof(u16);
514 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
516 writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR);
517 spi->tx_len -= sizeof(u8);
521 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
526 * @spi: pointer to the spi controller data structure
531 static void stm32h7_spi_write_txfifo(struct stm32_spi *spi)
533 while ((spi->tx_len > 0) &&
534 (readl_relaxed(spi->base + STM32H7_SPI_SR) &
536 u32 offs = spi->cur_xferlen - spi->tx_len;
538 if (spi->tx_len >= sizeof(u32)) {
539 const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs);
541 writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR);
542 spi->tx_len -= sizeof(u32);
543 } else if (spi->tx_len >= sizeof(u16)) {
544 const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs);
546 writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR);
547 spi->tx_len -= sizeof(u16);
549 const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs);
551 writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR);
552 spi->tx_len -= sizeof(u8);
556 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len);
561 * @spi: pointer to the spi controller data structure
566 static void stm32f4_spi_read_rx(struct stm32_spi *spi)
568 if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) &
570 u32 offs = spi->cur_xferlen - spi->rx_len;
572 if (spi->cur_bpw == 16) {
573 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
575 *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR);
576 spi->rx_len -= sizeof(u16);
578 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
580 *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR);
581 spi->rx_len -= sizeof(u8);
585 dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len);
590 * @spi: pointer to the spi controller data structure
595 static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi)
597 u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
600 while ((spi->rx_len > 0) &&
604 u32 offs = spi->cur_xferlen - spi->rx_len;
606 if ((spi->rx_len >= sizeof(u32)) ||
608 u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs);
610 *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR);
611 spi->rx_len -= sizeof(u32);
612 } else if ((spi->rx_len >= sizeof(u16)) ||
614 (rxplvl >= 2 || spi->cur_bpw > 8))) {
615 u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs);
617 *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR);
618 spi->rx_len -= sizeof(u16);
620 u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs);
622 *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR);
623 spi->rx_len -= sizeof(u8);
626 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
630 dev_dbg(spi->dev, "%s: %d bytes left (sr=%08x)\n",
631 __func__, spi->rx_len, sr);
636 * @spi: pointer to the spi controller data structure
638 static void stm32_spi_enable(struct stm32_spi *spi)
640 dev_dbg(spi->dev, "enable controller\n");
642 stm32_spi_set_bits(spi, spi->cfg->regs->en.reg,
643 spi->cfg->regs->en.mask);
648 * @spi: pointer to the spi controller data structure
650 static void stm32f4_spi_disable(struct stm32_spi *spi)
655 dev_dbg(spi->dev, "disable controller\n");
657 spin_lock_irqsave(&spi->lock, flags);
659 if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) &
661 spin_unlock_irqrestore(&spi->lock, flags);
666 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE |
671 if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR,
674 dev_warn(spi->dev, "disabling condition timeout\n");
677 if (spi->cur_usedma && spi->dma_tx)
678 dmaengine_terminate_async(spi->dma_tx);
679 if (spi->cur_usedma && spi->dma_rx)
680 dmaengine_terminate_async(spi->dma_rx);
682 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE);
684 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN |
688 readl_relaxed(spi->base + STM32F4_SPI_DR);
689 readl_relaxed(spi->base + STM32F4_SPI_SR);
691 spin_unlock_irqrestore(&spi->lock, flags);
696 * @spi: pointer to the spi controller data structure
700 static void stm32h7_spi_disable(struct stm32_spi *spi)
705 dev_dbg(spi->dev, "disable controller\n");
707 spin_lock_irqsave(&spi->lock, flags);
709 cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1);
712 spin_unlock_irqrestore(&spi->lock, flags);
717 if (spi->cur_half_period)
718 udelay(spi->cur_half_period);
720 if (spi->cur_usedma && spi->dma_tx)
721 dmaengine_terminate_async(spi->dma_tx);
722 if (spi->cur_usedma && spi->dma_rx)
723 dmaengine_terminate_async(spi->dma_rx);
725 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE);
727 stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN |
731 writel_relaxed(0, spi->base + STM32H7_SPI_IER);
732 writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR);
734 spin_unlock_irqrestore(&spi->lock, flags);
740 * @spi_dev: pointer to the spi device
741 * @transfer: pointer to spi transfer
751 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
753 if (spi->cfg->has_fifo)
754 dma_size = spi->fifo_size;
758 dev_dbg(spi->dev, "%s: %s\n", __func__,
772 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
776 spin_lock(&spi->lock);
778 sr = readl_relaxed(spi->base + STM32F4_SPI_SR);
785 if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX ||
786 spi->cur_comm == SPI_3WIRE_TX)) {
792 if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX ||
793 spi->cur_comm == SPI_SIMPLEX_RX ||
794 spi->cur_comm == SPI_3WIRE_RX)) {
801 dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr);
802 spin_unlock(&spi->lock);
807 dev_warn(spi->dev, "Overrun: received value discarded\n");
810 readl_relaxed(spi->base + STM32F4_SPI_DR);
811 readl_relaxed(spi->base + STM32F4_SPI_SR);
823 if (spi->tx_buf)
824 stm32f4_spi_write_tx(spi);
825 if (spi->tx_len == 0)
830 stm32f4_spi_read_rx(spi);
831 if (spi->rx_len == 0)
833 else if (spi->tx_buf)/* Load data for discontinuous mode */
834 stm32f4_spi_write_tx(spi);
840 stm32_spi_clr_bits(spi, STM32F4_SPI_CR2,
844 spin_unlock(&spi->lock);
848 spin_unlock(&spi->lock);
860 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
863 stm32f4_spi_disable(spi);
876 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
881 spin_lock_irqsave(&spi->lock, flags);
883 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
884 ier = readl_relaxed(spi->base + STM32H7_SPI_IER);
897 if ((spi->cur_comm == SPI_FULL_DUPLEX) && !spi->cur_usedma)
901 dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
903 spin_unlock_irqrestore(&spi->lock, flags);
913 dev_dbg_ratelimited(spi->dev, "Communication suspended\n");
914 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
915 stm32h7_spi_read_rxfifo(spi);
920 if (spi->cur_usedma)
925 dev_warn(spi->dev, "Mode fault: transfer aborted\n");
930 dev_err(spi->dev, "Overrun: RX data lost\n");
935 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
936 stm32h7_spi_read_rxfifo(spi);
937 if (!spi->cur_usedma ||
938 (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX))
943 if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0)))
944 stm32h7_spi_write_txfifo(spi);
947 if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
948 stm32h7_spi_read_rxfifo(spi);
950 writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR);
952 spin_unlock_irqrestore(&spi->lock, flags);
955 stm32h7_spi_disable(spi);
965 * @msg: pointer to spi message
970 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
971 struct spi_device *spi_dev = msg->spi;
977 spi->cur_midi = 0;
978 if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi))
979 dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi);
982 setb |= spi->cfg->regs->cpol.mask;
984 clrb |= spi->cfg->regs->cpol.mask;
987 setb |= spi->cfg->regs->cpha.mask;
989 clrb |= spi->cfg->regs->cpha.mask;
992 setb |= spi->cfg->regs->lsb_first.mask;
994 clrb |= spi->cfg->regs->lsb_first.mask;
996 if (STM32_SPI_DEVICE_MODE(spi) && spi_dev->mode & SPI_CS_HIGH)
997 setb |= spi->cfg->regs->cs_high.mask;
999 clrb |= spi->cfg->regs->cs_high.mask;
1001 dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n",
1011 if (spi->cfg->set_number_of_data) {
1021 spin_lock_irqsave(&spi->lock, flags);
1026 (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) &
1028 spi->base + spi->cfg->regs->cpol.reg);
1030 spin_unlock_irqrestore(&spi->lock, flags);
1037 * @data: pointer to the spi controller data structure
1043 struct stm32_spi *spi = data;
1045 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1046 spi_finalize_current_transfer(spi->ctrl);
1047 stm32f4_spi_disable(spi);
1053 * @data: pointer to the spi controller data structure
1059 struct stm32_spi *spi = data;
1061 spi_finalize_current_transfer(spi->ctrl);
1062 spi->cfg->disable(spi);
1068 * @spi: pointer to the spi controller data structure
1072 static void stm32_spi_dma_config(struct stm32_spi *spi,
1079 if (spi->cur_bpw <= 8)
1081 else if (spi->cur_bpw <= 16)
1086 if (spi->cfg->has_fifo) {
1088 if (spi->cur_fthlv == 2)
1091 maxburst = spi->cur_fthlv;
1099 dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg;
1103 dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n",
1106 dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg;
1110 dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n",
1118 * @spi: pointer to the spi controller data structure
1123 static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi)
1129 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) {
1131 } else if (spi->cur_comm == SPI_FULL_DUPLEX ||
1132 spi->cur_comm == SPI_SIMPLEX_RX ||
1133 spi->cur_comm == SPI_3WIRE_RX) {
1143 spin_lock_irqsave(&spi->lock, flags);
1145 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2);
1147 stm32_spi_enable(spi);
1150 if (spi->tx_buf)
1151 stm32f4_spi_write_tx(spi);
1153 spin_unlock_irqrestore(&spi->lock, flags);
1161 * @spi: pointer to the spi controller data structure
1166 static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi)
1172 if (spi->tx_buf && spi->rx_buf) /* Full Duplex */
1174 else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */
1176 else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */
1183 spin_lock_irqsave(&spi->lock, flags);
1185 stm32_spi_enable(spi);
1188 if (spi->tx_buf)
1189 stm32h7_spi_write_txfifo(spi);
1191 if (STM32_SPI_MASTER_MODE(spi))
1192 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1194 writel_relaxed(ier, spi->base + STM32H7_SPI_IER);
1196 spin_unlock_irqrestore(&spi->lock, flags);
1204 * @spi: pointer to the spi controller data structure
1206 static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi)
1209 if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX ||
1210 spi->cur_comm == SPI_FULL_DUPLEX) {
1216 stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE);
1219 stm32_spi_enable(spi);
1225 * @spi: pointer to the spi controller data structure
1227 static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi)
1232 if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX)
1235 stm32_spi_set_bits(spi, STM32H7_SPI_IER, ier);
1237 stm32_spi_enable(spi);
1239 if (STM32_SPI_MASTER_MODE(spi))
1240 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART);
1245 * @spi: pointer to the spi controller data structure
1251 static int stm32_spi_transfer_one_dma(struct stm32_spi *spi,
1258 spin_lock_irqsave(&spi->lock, flags);
1261 if (spi->rx_buf && spi->dma_rx) {
1262 stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM);
1263 dmaengine_slave_config(spi->dma_rx, &rx_dma_conf);
1266 stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1267 spi->cfg->regs->dma_rx_en.mask);
1270 spi->dma_rx, xfer->rx_sg.sgl,
1277 if (spi->tx_buf && spi->dma_tx) {
1278 stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV);
1279 dmaengine_slave_config(spi->dma_tx, &tx_dma_conf);
1282 spi->dma_tx, xfer->tx_sg.sgl,
1288 if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) ||
1289 (spi->rx_buf && spi->dma_rx && !rx_dma_desc))
1292 if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc))
1296 rx_dma_desc->callback = spi->cfg->dma_rx_cb;
1297 rx_dma_desc->callback_param = spi;
1300 dev_err(spi->dev, "Rx DMA submit failed\n");
1304 dma_async_issue_pending(spi->dma_rx);
1308 if (spi->cur_comm == SPI_SIMPLEX_TX ||
1309 spi->cur_comm == SPI_3WIRE_TX) {
1310 tx_dma_desc->callback = spi->cfg->dma_tx_cb;
1311 tx_dma_desc->callback_param = spi;
1315 dev_err(spi->dev, "Tx DMA submit failed\n");
1319 dma_async_issue_pending(spi->dma_tx);
1322 stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg,
1323 spi->cfg->regs->dma_tx_en.mask);
1326 spi->cfg->transfer_one_dma_start(spi);
1328 spin_unlock_irqrestore(&spi->lock, flags);
1333 if (spi->dma_rx)
1334 dmaengine_terminate_sync(spi->dma_rx);
1337 stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg,
1338 spi->cfg->regs->dma_rx_en.mask);
1340 spin_unlock_irqrestore(&spi->lock, flags);
1342 dev_info(spi->dev, "DMA issue: fall back to irq transfer\n");
1344 spi->cur_usedma = false;
1345 return spi->cfg->transfer_one_irq(spi);
1350 * @spi: pointer to the spi controller data structure
1352 static void stm32f4_spi_set_bpw(struct stm32_spi *spi)
1354 if (spi->cur_bpw == 16)
1355 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1357 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF);
1362 * @spi: pointer to the spi controller data structure
1364 static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
1369 bpw = spi->cur_bpw - 1;
1374 spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
1375 fthlv = spi->cur_fthlv - 1;
1381 (readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
1383 spi->base + STM32H7_SPI_CFG1);
1388 * @spi: pointer to the spi controller data structure
1391 static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv)
1395 clrb |= spi->cfg->regs->br.mask;
1396 setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
1398 writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
1400 spi->base + spi->cfg->regs->br.reg);
1405 * @spi_dev: pointer to the spi device
1406 * @transfer: pointer to spi transfer
1436 * @spi: pointer to the spi controller data structure
1439 static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1442 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1447 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1451 stm32_spi_set_bits(spi, STM32F4_SPI_CR1,
1453 stm32_spi_clr_bits(spi, STM32F4_SPI_CR1,
1464 * @spi: pointer to the spi controller data structure
1467 static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type)
1474 stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1477 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR);
1490 (readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1492 spi->base + STM32H7_SPI_CFG2);
1500 * @spi: pointer to the spi controller data structure
1503 static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len)
1508 if ((len > 1) && (spi->cur_midi > 0)) {
1509 u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
1511 DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
1516 dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n",
1521 writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) &
1523 spi->base + STM32H7_SPI_CFG2);
1528 * @spi: pointer to the spi controller data structure
1531 static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words)
1535 spi->base + STM32H7_SPI_CR2);
1547 * @spi: pointer to the spi controller data structure
1548 * @spi_dev: pointer to the spi device
1549 * @transfer: pointer to spi transfer
1551 static int stm32_spi_transfer_one_setup(struct stm32_spi *spi,
1560 spin_lock_irqsave(&spi->lock, flags);
1562 spi->cur_xferlen = transfer->len;
1564 spi->cur_bpw = transfer->bits_per_word;
1565 spi->cfg->set_bpw(spi);
1567 /* Update spi->cur_speed with real clock speed */
1568 if (STM32_SPI_MASTER_MODE(spi)) {
1569 mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
1570 spi->cfg->baud_rate_div_min,
1571 spi->cfg->baud_rate_div_max);
1577 transfer->speed_hz = spi->cur_speed;
1578 stm32_spi_set_mbr(spi, mbr);
1582 ret = spi->cfg->set_mode(spi, comm_type);
1586 spi->cur_comm = comm_type;
1588 if (STM32_SPI_MASTER_MODE(spi) && spi->cfg->set_data_idleness)
1589 spi->cfg->set_data_idleness(spi, transfer->len);
1591 if (spi->cur_bpw <= 8)
1593 else if (spi->cur_bpw <= 16)
1598 if (spi->cfg->set_number_of_data) {
1599 ret = spi->cfg->set_number_of_data(spi, nb_words);
1604 dev_dbg(spi->dev, "transfer communication mode set to %d\n",
1605 spi->cur_comm);
1606 dev_dbg(spi->dev,
1608 spi->cur_bpw, spi->cur_fthlv);
1609 if (STM32_SPI_MASTER_MODE(spi))
1610 dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed);
1611 dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n",
1612 spi->cur_xferlen, nb_words);
1613 dev_dbg(spi->dev, "dma %s\n",
1614 (spi->cur_usedma) ? "enabled" : "disabled");
1617 spin_unlock_irqrestore(&spi->lock, flags);
1625 * @spi_dev: pointer to the spi device
1626 * @transfer: pointer to spi transfer
1635 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1638 spi->tx_buf = transfer->tx_buf;
1639 spi->rx_buf = transfer->rx_buf;
1640 spi->tx_len = spi->tx_buf ? transfer->len : 0;
1641 spi->rx_len = spi->rx_buf ? transfer->len : 0;
1643 spi->cur_usedma = (ctrl->can_dma &&
1646 ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer);
1648 dev_err(spi->dev, "SPI transfer setup failed\n");
1652 if (spi->cur_usedma)
1653 return stm32_spi_transfer_one_dma(spi, transfer);
1655 return spi->cfg->transfer_one_irq(spi);
1661 * @msg: pointer to the spi message
1666 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1668 spi->cfg->disable(spi);
1675 * @spi: pointer to the spi controller data structure
1677 static int stm32f4_spi_config(struct stm32_spi *spi)
1681 spin_lock_irqsave(&spi->lock, flags);
1684 stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR,
1694 stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI |
1699 spin_unlock_irqrestore(&spi->lock, flags);
1706 * @spi: pointer to the spi controller data structure
1708 static int stm32h7_spi_config(struct stm32_spi *spi)
1713 spin_lock_irqsave(&spi->lock, flags);
1716 stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR,
1719 if (STM32_SPI_DEVICE_MODE(spi)) {
1739 stm32_spi_set_bits(spi, STM32H7_SPI_CR1, cr1);
1740 stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, cfg2);
1742 spin_unlock_irqrestore(&spi->lock, flags);
1792 { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg },
1793 { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg },
1807 struct stm32_spi *spi;
1815 device_mode = of_property_read_bool(np, "spi-slave");
1817 dev_err(&pdev->dev, "spi-slave not supported\n");
1826 dev_err(&pdev->dev, "spi controller allocation failed\n");
1831 spi = spi_controller_get_devdata(ctrl);
1832 spi->dev = &pdev->dev;
1833 spi->ctrl = ctrl;
1834 spi->device_mode = device_mode;
1835 spin_lock_init(&spi->lock);
1837 spi->cfg = cfg;
1839 spi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1840 if (IS_ERR(spi->base))
1841 return PTR_ERR(spi->base);
1843 spi->phys_addr = (dma_addr_t)res->start;
1845 spi->irq = platform_get_irq(pdev, 0);
1846 if (spi->irq <= 0)
1847 return spi->irq;
1849 ret = devm_request_threaded_irq(&pdev->dev, spi->irq,
1850 spi->cfg->irq_handler_event,
1851 spi->cfg->irq_handler_thread,
1854 dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq,
1859 spi->clk = devm_clk_get(&pdev->dev, NULL);
1860 if (IS_ERR(spi->clk)) {
1861 ret = PTR_ERR(spi->clk);
1866 ret = clk_prepare_enable(spi->clk);
1871 spi->clk_rate = clk_get_rate(spi->clk);
1872 if (!spi->clk_rate) {
1891 if (spi->cfg->has_fifo)
1892 spi->fifo_size = spi->cfg->get_fifo_size(spi);
1894 ret = spi->cfg->config(spi);
1906 ctrl->bits_per_word_mask = spi->cfg->get_bpw_mask(spi);
1907 ctrl->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
1908 ctrl->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
1913 ctrl->flags = spi->cfg->flags;
1914 if (STM32_SPI_DEVICE_MODE(spi))
1917 spi->dma_tx = dma_request_chan(spi->dev, "tx");
1918 if (IS_ERR(spi->dma_tx)) {
1919 ret = PTR_ERR(spi->dma_tx);
1920 spi->dma_tx = NULL;
1926 ctrl->dma_tx = spi->dma_tx;
1929 spi->dma_rx = dma_request_chan(spi->dev, "rx");
1930 if (IS_ERR(spi->dma_rx)) {
1931 ret = PTR_ERR(spi->dma_rx);
1932 spi->dma_rx = NULL;
1938 ctrl->dma_rx = spi->dma_rx;
1941 if (spi->dma_tx || spi->dma_rx)
1953 dev_err(&pdev->dev, "spi controller registration failed: %d\n",
1962 STM32_SPI_MASTER_MODE(spi) ? "master" : "device");
1972 if (spi->dma_tx)
1973 dma_release_channel(spi->dma_tx);
1974 if (spi->dma_rx)
1975 dma_release_channel(spi->dma_rx);
1977 clk_disable_unprepare(spi->clk);
1985 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
1990 spi->cfg->disable(spi);
2002 clk_disable_unprepare(spi->clk);
2011 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2013 clk_disable_unprepare(spi->clk);
2021 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2028 return clk_prepare_enable(spi->clk);
2046 struct stm32_spi *spi = spi_controller_get_devdata(ctrl);
2055 clk_disable_unprepare(spi->clk);
2065 spi->cfg->config(spi);