Lines Matching refs:val
195 u32 val, us;
199 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
200 val & SPRD_SPI_TX_END_IRQ, 0, us);
206 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_STS2, val,
207 !(val & SPRD_SPI_TX_BUSY), 0, us);
220 u32 val, us;
224 ret = readl_relaxed_poll_timeout(ss->base + SPRD_SPI_INT_RAW_STS, val,
225 val & SPRD_SPI_RX_END_IRQ, 0, us);
248 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL1);
250 val &= ~SPRD_SPI_RTX_MD_MASK;
251 writel_relaxed(val, ss->base + SPRD_SPI_CTL1);
256 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
259 val &= ~(SPRD_SPI_CHNL_LEN_MASK << SPRD_SPI_CHNL_LEN);
260 val |= bits << SPRD_SPI_CHNL_LEN;
261 writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
266 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL8);
269 val &= ~SPRD_SPI_TX_LEN_H_MASK;
270 val |= length >> SPRD_SPI_TX_LEN_H_OFFSET;
271 writel_relaxed(val, ss->base + SPRD_SPI_CTL8);
273 val = length & SPRD_SPI_TX_LEN_L_MASK;
274 writel_relaxed(val, ss->base + SPRD_SPI_CTL9);
279 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL10);
282 val &= ~SPRD_SPI_RX_LEN_H_MASK;
283 val |= length >> SPRD_SPI_RX_LEN_H_OFFSET;
284 writel_relaxed(val, ss->base + SPRD_SPI_CTL10);
286 val = length & SPRD_SPI_RX_LEN_L_MASK;
287 writel_relaxed(val, ss->base + SPRD_SPI_CTL11);
294 u32 val;
296 val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
299 val &= ~SPRD_SPI_CS0_VALID;
300 writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
302 val |= SPRD_SPI_CSN_MASK;
303 writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
309 u32 val;
312 val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
313 val &= ~(SPRD_SPI_START_RX | SPRD_SPI_ONLY_RECV_MASK);
314 writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
317 val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
318 val |= len & SPRD_SPI_ONLY_RECV_MASK;
319 writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
322 val = readl_relaxed(ss->base + SPRD_SPI_CTL4);
323 val |= SPRD_SPI_START_RX;
324 writel_relaxed(val, ss->base + SPRD_SPI_CTL4);
458 u32 val;
464 val = readl_relaxed(ss->base + SPRD_SPI_INT_EN);
465 writel_relaxed(val | SPRD_SPI_TX_END_INT_EN |
477 u32 val = readl_relaxed(ss->base + SPRD_SPI_CTL2);
480 val |= SPRD_SPI_DMA_EN;
482 val &= ~SPRD_SPI_DMA_EN;
484 writel_relaxed(val, ss->base + SPRD_SPI_CTL2);
668 u32 val;
673 val = readl_relaxed(ss->base + SPRD_SPI_CTL0);
674 val &= ~(SPRD_SPI_SCK_REV | SPRD_SPI_NG_TX | SPRD_SPI_NG_RX);
676 val |= ss->hw_mode & SPI_CPHA ? SPRD_SPI_NG_RX : SPRD_SPI_NG_TX;
677 val |= ss->hw_mode & SPI_CPOL ? SPRD_SPI_SCK_REV : 0;
678 writel_relaxed(val, ss->base + SPRD_SPI_CTL0);
696 val = readl_relaxed(ss->base + SPRD_SPI_CTL7);
697 val &= ~SPRD_SPI_MODE_MASK;
700 val |= SPRD_SPI_3WIRE_MODE << SPRD_SPI_MODE_OFFSET;
702 val |= SPRD_SPI_4WIRE_MODE << SPRD_SPI_MODE_OFFSET;
705 val |= SPRD_SPI_DATA_LINE2_EN;
707 val &= ~SPRD_SPI_DATA_LINE2_EN;
709 writel_relaxed(val, ss->base + SPRD_SPI_CTL7);
719 u32 val, mode = 0;
767 val = readl_relaxed(ss->base + SPRD_SPI_CTL1);
768 val &= ~SPRD_SPI_RTX_MD_MASK;
774 writel_relaxed(val | mode, ss->base + SPRD_SPI_CTL1);
817 u32 val = readl_relaxed(ss->base + SPRD_SPI_INT_MASK_STS);
819 if (val & SPRD_SPI_MASK_TX_END) {
827 if (val & SPRD_SPI_MASK_RX_END) {