Lines Matching defs:spi
15 #include <linux/spi/spi.h>
99 static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value)
101 iowrite32(value, spi->regs + offset);
104 static u32 sifive_spi_read(struct sifive_spi *spi, int offset)
106 return ioread32(spi->regs + offset);
109 static void sifive_spi_init(struct sifive_spi *spi)
112 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
115 sifive_spi_write(spi, SIFIVE_SPI_REG_TXMARK, 1);
116 sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK, 0);
119 sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY0,
122 sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY1,
127 sifive_spi_write(spi, SIFIVE_SPI_REG_FCTRL, 0);
133 struct sifive_spi *spi = spi_controller_get_devdata(host);
134 struct spi_device *device = msg->spi;
138 spi->cs_inactive &= ~BIT(spi_get_chipselect(device, 0));
140 spi->cs_inactive |= BIT(spi_get_chipselect(device, 0));
141 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
144 sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, spi_get_chipselect(device, 0));
147 sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE,
155 struct sifive_spi *spi = spi_controller_get_devdata(device->controller);
161 sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, is_high ?
167 sifive_spi_prep_transfer(struct sifive_spi *spi, struct spi_device *device,
174 cr = DIV_ROUND_UP(clk_get_rate(spi->clk) >> 1, t->speed_hz) - 1;
176 sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, cr);
197 sifive_spi_write(spi, SIFIVE_SPI_REG_FMT, cr);
205 return 1600000 * spi->fifo_depth <= t->speed_hz * mode;
210 struct sifive_spi *spi = dev_id;
211 u32 ip = sifive_spi_read(spi, SIFIVE_SPI_REG_IP);
215 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
216 complete(&spi->done);
223 static void sifive_spi_wait(struct sifive_spi *spi, u32 bit, int poll)
229 cr = sifive_spi_read(spi, SIFIVE_SPI_REG_IP);
232 reinit_completion(&spi->done);
233 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, bit);
234 wait_for_completion(&spi->done);
238 static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
240 WARN_ON_ONCE((sifive_spi_read(spi, SIFIVE_SPI_REG_TXDATA)
242 sifive_spi_write(spi, SIFIVE_SPI_REG_TXDATA,
246 static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
248 u32 data = sifive_spi_read(spi, SIFIVE_SPI_REG_RXDATA);
258 struct sifive_spi *spi = spi_controller_get_devdata(host);
259 int poll = sifive_spi_prep_transfer(spi, device, t);
265 unsigned int n_words = min(remaining_words, spi->fifo_depth);
270 sifive_spi_tx(spi, tx_ptr++);
274 sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK,
276 sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM, poll);
280 sifive_spi_rx(spi, rx_ptr++);
283 sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM, poll);
294 struct sifive_spi *spi;
305 spi = spi_controller_get_devdata(host);
306 init_completion(&spi->done);
309 spi->regs = devm_platform_ioremap_resource(pdev, 0);
310 if (IS_ERR(spi->regs)) {
311 ret = PTR_ERR(spi->regs);
315 spi->clk = devm_clk_get(&pdev->dev, NULL);
316 if (IS_ERR(spi->clk)) {
318 ret = PTR_ERR(spi->clk);
331 &spi->fifo_depth);
333 spi->fifo_depth = SIFIVE_SPI_DEFAULT_DEPTH;
346 ret = clk_prepare_enable(spi->clk);
353 spi->cs_inactive = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
354 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU);
355 cs_bits = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
356 sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
365 dev_err(&pdev->dev, "Invalid number of spi targets\n");
389 sifive_spi_init(spi);
393 dev_name(&pdev->dev), spi);
411 clk_disable_unprepare(spi->clk);
421 struct sifive_spi *spi = spi_controller_get_devdata(host);
424 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
425 clk_disable_unprepare(spi->clk);
431 struct sifive_spi *spi = spi_controller_get_devdata(host);
439 sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
441 clk_disable_unprepare(spi->clk);
449 struct sifive_spi *spi = spi_controller_get_devdata(host);
452 ret = clk_prepare_enable(spi->clk);
457 clk_disable_unprepare(spi->clk);