Lines Matching defs:set
220 u32 clr, u32 set)
222 u32 mask = clr | set;
227 data |= set;
231 (data & mask) == set, 1, 100);
557 u32 clr, set, tmp;
568 set = SIMDR1_SYNCMD_SPI;
572 set |= BIT(SIMDR1_SYNCAC_SHIFT);
575 sh_msiof_write(p, SITMDR1, tmp | set | SIMDR1_TRMD | SITMDR1_PCON);
577 sh_msiof_write(p, SIRMDR1, tmp | set);
1203 /* The DMA engine uses the second register set, if present */