Lines Matching refs:csi
104 static void rzv2m_csi_reg_write_bit(const struct rzv2m_csi_priv *csi,
113 tmp = (readl(csi->base + reg_offs) & ~bit_mask) | value;
114 writel(tmp, csi->base + reg_offs);
117 static int rzv2m_csi_sw_reset(struct rzv2m_csi_priv *csi, int assert)
121 rzv2m_csi_reg_write_bit(csi, CSI_CNT, CSI_CNT_CSIRST, assert);
126 return readl_poll_timeout(csi->base + CSI_MODE, reg,
131 static int rzv2m_csi_start_stop_operation(const struct rzv2m_csi_priv *csi,
136 rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_CSIE, enable);
141 return readl_poll_timeout(csi->base + CSI_MODE, reg,
146 static int rzv2m_csi_fill_txfifo(struct rzv2m_csi_priv *csi)
150 if (readl(csi->base + CSI_OFIFOL))
153 if (csi->bytes_per_word == 2) {
154 const u16 *buf = csi->txbuf;
156 for (i = 0; i < csi->words_to_transfer; i++)
157 writel(buf[i], csi->base + CSI_OFIFO);
159 const u8 *buf = csi->txbuf;
161 for (i = 0; i < csi->words_to_transfer; i++)
162 writel(buf[i], csi->base + CSI_OFIFO);
165 csi->txbuf += csi->bytes_to_transfer;
166 csi->bytes_sent += csi->bytes_to_transfer;
171 static int rzv2m_csi_read_rxfifo(struct rzv2m_csi_priv *csi)
175 if (readl(csi->base + CSI_IFIFOL) != csi->bytes_to_transfer)
178 if (csi->bytes_per_word == 2) {
179 u16 *buf = csi->rxbuf;
181 for (i = 0; i < csi->words_to_transfer; i++)
182 buf[i] = (u16)readl(csi->base + CSI_IFIFO);
184 u8 *buf = csi->rxbuf;
186 for (i = 0; i < csi->words_to_transfer; i++)
187 buf[i] = (u8)readl(csi->base + CSI_IFIFO);
190 csi->rxbuf += csi->bytes_to_transfer;
191 csi->bytes_received += csi->bytes_to_transfer;
196 static inline void rzv2m_csi_calc_current_transfer(struct rzv2m_csi_priv *csi)
198 unsigned int bytes_transferred = max(csi->bytes_received, csi->bytes_sent);
199 unsigned int bytes_remaining = csi->buffer_len - bytes_transferred;
202 if (csi->txbuf)
212 if (csi->bytes_per_word == 2)
221 csi->words_to_transfer = rounddown_pow_of_two(to_transfer);
223 if (csi->bytes_per_word == 2)
224 csi->bytes_to_transfer = csi->words_to_transfer << 1;
226 csi->bytes_to_transfer = csi->words_to_transfer;
229 static inline void rzv2m_csi_set_rx_fifo_trigger_level(struct rzv2m_csi_priv *csi)
231 rzv2m_csi_reg_write_bit(csi, CSI_FIFOTRG, CSI_FIFOTRG_R_TRG,
232 ilog2(csi->words_to_transfer));
235 static inline void rzv2m_csi_enable_rx_trigger(struct rzv2m_csi_priv *csi,
238 rzv2m_csi_reg_write_bit(csi, CSI_CNT, CSI_CNT_R_TRGEN, enable);
241 static void rzv2m_csi_disable_irqs(const struct rzv2m_csi_priv *csi,
244 u32 cnt = readl(csi->base + CSI_CNT);
246 writel(cnt & ~enable_bits, csi->base + CSI_CNT);
249 static void rzv2m_csi_disable_all_irqs(struct rzv2m_csi_priv *csi)
251 rzv2m_csi_disable_irqs(csi, CSI_CNT_R_TRGR_E | CSI_CNT_T_TRGR_E |
256 static inline void rzv2m_csi_clear_irqs(struct rzv2m_csi_priv *csi, u32 irqs)
258 writel(irqs, csi->base + CSI_INT);
261 static void rzv2m_csi_clear_all_irqs(struct rzv2m_csi_priv *csi)
263 rzv2m_csi_clear_irqs(csi, CSI_INT_UNDER | CSI_INT_OVERF |
268 static void rzv2m_csi_enable_irqs(struct rzv2m_csi_priv *csi, u32 enable_bits)
270 u32 cnt = readl(csi->base + CSI_CNT);
272 writel(cnt | enable_bits, csi->base + CSI_CNT);
275 static int rzv2m_csi_wait_for_interrupt(struct rzv2m_csi_priv *csi,
280 rzv2m_csi_enable_irqs(csi, enable_bits);
282 ret = wait_event_timeout(csi->wait,
283 ((csi->status & wait_mask) == wait_mask) ||
284 csi->errors, HZ);
286 rzv2m_csi_disable_irqs(csi, enable_bits);
288 if (csi->errors)
297 static int rzv2m_csi_wait_for_tx_empty(struct rzv2m_csi_priv *csi)
301 if (readl(csi->base + CSI_OFIFOL) == 0)
304 ret = rzv2m_csi_wait_for_interrupt(csi, CSI_INT_TREND, CSI_CNT_TREND_E);
306 csi->errors |= TX_TIMEOUT_ERROR;
311 static inline int rzv2m_csi_wait_for_rx_ready(struct rzv2m_csi_priv *csi)
315 if (readl(csi->base + CSI_IFIFOL) == csi->bytes_to_transfer)
318 ret = rzv2m_csi_wait_for_interrupt(csi, CSI_INT_R_TRGR,
321 csi->errors |= RX_TIMEOUT_ERROR;
328 struct rzv2m_csi_priv *csi = data;
330 csi->status = readl(csi->base + CSI_INT);
331 rzv2m_csi_disable_irqs(csi, csi->status);
333 if (csi->status & CSI_INT_OVERF)
334 csi->errors |= OVERFLOW_ERROR;
335 if (csi->status & CSI_INT_UNDER)
336 csi->errors |= UNDERRUN_ERROR;
338 wake_up(&csi->wait);
343 static void rzv2m_csi_setup_clock(struct rzv2m_csi_priv *csi, u32 spi_hz)
345 unsigned long csiclk_rate = clk_get_rate(csi->csiclk);
346 unsigned long pclk_rate = clk_get_rate(csi->pclk);
355 clk_set_rate(csi->csiclk, csiclk_rate >> 1);
356 csiclk_rate = clk_get_rate(csi->csiclk);
358 clk_set_rate(csi->csiclk, csiclk_rate << 1);
359 csiclk_rate = clk_get_rate(csi->csiclk);
368 dev_dbg(csi->dev, "SPI clk rate is %ldHz\n", csiclk_rate / (cks << 1));
370 rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_CKS, cks);
373 static void rzv2m_csi_setup_operating_mode(struct rzv2m_csi_priv *csi,
378 rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_TRMD, 0);
381 rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_TRMD, 1);
383 csi->bytes_per_word = t->bits_per_word / 8;
384 rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_CCL,
385 csi->bytes_per_word == 2);
390 struct rzv2m_csi_priv *csi = spi_controller_get_devdata(spi->controller);
393 rzv2m_csi_sw_reset(csi, 0);
395 writel(CSI_MODE_SETUP, csi->base + CSI_MODE);
398 rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_MODE,
402 rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_DIR,
406 rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_SLAVE, 0);
409 ret = rzv2m_csi_sw_reset(csi, 1);
412 rzv2m_csi_sw_reset(csi, 0);
418 rzv2m_csi_start_stop_operation(csi, 1, false);
420 rzv2m_csi_start_stop_operation(csi, 0, false);
425 static int rzv2m_csi_pio_transfer(struct rzv2m_csi_priv *csi)
427 bool tx_completed = !csi->txbuf;
428 bool rx_completed = !csi->rxbuf;
432 writel(0, csi->base + CSI_OFIFOL);
434 csi->bytes_sent = 0;
435 csi->bytes_received = 0;
436 csi->errors = 0;
438 rzv2m_csi_disable_all_irqs(csi);
439 rzv2m_csi_clear_all_irqs(csi);
440 rzv2m_csi_enable_rx_trigger(csi, true);
450 rzv2m_csi_calc_current_transfer(csi);
451 rzv2m_csi_set_rx_fifo_trigger_level(csi);
453 rzv2m_csi_enable_irqs(csi, CSI_INT_OVERF | CSI_INT_UNDER);
456 writel(0, csi->base + CSI_IFIFOL);
458 writel(readl(csi->base + CSI_INT), csi->base + CSI_INT);
459 csi->status = 0;
461 rzv2m_csi_start_stop_operation(csi, 1, false);
464 if (csi->txbuf) {
465 ret = rzv2m_csi_fill_txfifo(csi);
469 ret = rzv2m_csi_wait_for_tx_empty(csi);
473 if (csi->bytes_sent == csi->buffer_len)
480 * csi->rxbuf.
482 ret = rzv2m_csi_wait_for_rx_ready(csi);
487 if (csi->rxbuf) {
488 rzv2m_csi_start_stop_operation(csi, 0, false);
490 ret = rzv2m_csi_read_rxfifo(csi);
494 if (csi->bytes_received == csi->buffer_len)
498 ret = rzv2m_csi_start_stop_operation(csi, 0, true);
502 if (csi->errors) {
508 rzv2m_csi_start_stop_operation(csi, 0, true);
511 rzv2m_csi_disable_all_irqs(csi);
512 rzv2m_csi_enable_rx_trigger(csi, false);
513 rzv2m_csi_clear_all_irqs(csi);
522 struct rzv2m_csi_priv *csi = spi_controller_get_devdata(controller);
523 struct device *dev = csi->dev;
526 csi->txbuf = transfer->tx_buf;
527 csi->rxbuf = transfer->rx_buf;
528 csi->buffer_len = transfer->len;
530 rzv2m_csi_setup_operating_mode(csi, transfer);
532 rzv2m_csi_setup_clock(csi, transfer->speed_hz);
534 ret = rzv2m_csi_pio_transfer(csi);
536 if (csi->errors & UNDERRUN_ERROR)
538 if (csi->errors & OVERFLOW_ERROR)
540 if (csi->errors & TX_TIMEOUT_ERROR)
542 if (csi->errors & RX_TIMEOUT_ERROR)
553 struct rzv2m_csi_priv *csi;
558 controller = devm_spi_alloc_host(dev, sizeof(*csi));
562 csi = spi_controller_get_devdata(controller);
563 platform_set_drvdata(pdev, csi);
565 csi->dev = dev;
566 csi->controller = controller;
568 csi->base = devm_platform_ioremap_resource(pdev, 0);
569 if (IS_ERR(csi->base))
570 return PTR_ERR(csi->base);
576 csi->csiclk = devm_clk_get(dev, "csiclk");
577 if (IS_ERR(csi->csiclk))
578 return dev_err_probe(dev, PTR_ERR(csi->csiclk),
581 csi->pclk = devm_clk_get(dev, "pclk");
582 if (IS_ERR(csi->pclk))
583 return dev_err_probe(dev, PTR_ERR(csi->pclk),
590 init_waitqueue_head(&csi->wait);
601 dev_name(dev), csi);
613 ret = rzv2m_csi_sw_reset(csi, 1);
617 ret = clk_prepare_enable(csi->csiclk);
623 clk_disable_unprepare(csi->csiclk);
632 struct rzv2m_csi_priv *csi = platform_get_drvdata(pdev);
634 spi_unregister_controller(csi->controller);
635 rzv2m_csi_sw_reset(csi, 1);
636 clk_disable_unprepare(csi->csiclk);
640 { .compatible = "renesas,rzv2m-csi" },