Lines Matching refs:rspi
27 #include <linux/spi/rspi.h>
200 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
202 iowrite8(data, rspi->addr + offset);
205 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
207 iowrite16(data, rspi->addr + offset);
210 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
212 iowrite32(data, rspi->addr + offset);
215 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
217 return ioread8(rspi->addr + offset);
220 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
222 return ioread16(rspi->addr + offset);
225 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
227 if (rspi->byte_access)
228 rspi_write8(rspi, data, RSPI_SPDR);
230 rspi_write16(rspi, data, RSPI_SPDR);
233 static u16 rspi_read_data(const struct rspi_data *rspi)
235 if (rspi->byte_access)
236 return rspi_read8(rspi, RSPI_SPDR);
238 return rspi_read16(rspi, RSPI_SPDR);
243 int (*set_config_register)(struct rspi_data *rspi, int access_size);
254 static void rspi_set_rate(struct rspi_data *rspi)
259 clksrc = clk_get_rate(rspi->clk);
260 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;
266 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
267 rspi->spcmd |= SPCMD_BRDV(brdv);
268 rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * (spbr + 1));
274 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
277 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
280 rspi_set_rate(rspi);
283 rspi_write8(rspi, 0, RSPI_SPDCR);
284 rspi->byte_access = 0;
287 rspi_write8(rspi, 0x00, RSPI_SPCKD);
288 rspi_write8(rspi, 0x00, RSPI_SSLND);
289 rspi_write8(rspi, 0x00, RSPI_SPND);
292 rspi_write8(rspi, 0x00, RSPI_SPCR2);
295 rspi_write8(rspi, 0, RSPI_SPSCR);
296 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
297 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
300 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
308 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
311 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
314 rspi_set_rate(rspi);
317 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
318 rspi->byte_access = 1;
321 rspi_write8(rspi, 0x00, RSPI_SPCKD);
322 rspi_write8(rspi, 0x00, RSPI_SSLND);
323 rspi_write8(rspi, 0x00, RSPI_SPND);
326 rspi_write8(rspi, 0, RSPI_SPSCR);
327 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
328 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
331 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
339 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
345 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
348 clksrc = clk_get_rate(rspi->clk);
349 if (rspi->speed_hz >= clksrc) {
351 rspi->speed_hz = clksrc;
353 spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz);
359 rspi->speed_hz = DIV_ROUND_UP(clksrc, (2U << brdv) * spbr);
361 rspi_write8(rspi, spbr, RSPI_SPBR);
362 rspi->spcmd |= SPCMD_BRDV(brdv);
365 rspi_write8(rspi, 0, RSPI_SPDCR);
366 rspi->byte_access = 1;
369 rspi_write8(rspi, 0x00, RSPI_SPCKD);
370 rspi_write8(rspi, 0x00, RSPI_SSLND);
371 rspi_write8(rspi, 0x00, RSPI_SPND);
375 rspi->spcmd |= SPCMD_SPB_8BIT;
377 rspi->spcmd |= SPCMD_SPB_16BIT;
379 rspi->spcmd |= SPCMD_SPB_32BIT;
381 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
384 rspi_write32(rspi, 0, QSPI_SPBMUL0);
387 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
389 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
392 rspi_write8(rspi, 0, RSPI_SPSCR);
393 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
396 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
401 static void qspi_update(const struct rspi_data *rspi, u8 mask, u8 val, u8 reg)
405 data = rspi_read8(rspi, reg);
408 rspi_write8(rspi, data, reg);
411 static unsigned int qspi_set_send_trigger(struct rspi_data *rspi,
420 qspi_update(rspi, SPBFCR_TXTRG_MASK,
424 qspi_update(rspi, SPBFCR_TXTRG_MASK,
431 static int qspi_set_receive_trigger(struct rspi_data *rspi, unsigned int len)
439 qspi_update(rspi, SPBFCR_RXTRG_MASK,
443 qspi_update(rspi, SPBFCR_RXTRG_MASK,
449 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
451 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
454 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
456 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
459 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
464 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
465 if (rspi->spsr & wait_mask)
468 rspi_enable_irq(rspi, enable_bit);
469 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
470 if (ret == 0 && !(rspi->spsr & wait_mask))
476 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
478 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
481 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
483 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
486 static int rspi_data_out(struct rspi_data *rspi, u8 data)
488 int error = rspi_wait_for_tx_empty(rspi);
490 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
493 rspi_write_data(rspi, data);
497 static int rspi_data_in(struct rspi_data *rspi)
502 error = rspi_wait_for_rx_full(rspi);
504 dev_err(&rspi->ctlr->dev, "receive timeout\n");
507 data = rspi_read_data(rspi);
511 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
516 int ret = rspi_data_out(rspi, *tx++);
521 int ret = rspi_data_in(rspi);
533 struct rspi_data *rspi = arg;
535 rspi->dma_callbacked = 1;
536 wake_up_interruptible(&rspi->wait);
539 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx,
550 desc_rx = dmaengine_prep_slave_sg(rspi->ctlr->dma_rx, rx->sgl,
559 desc_rx->callback_param = rspi;
570 desc_tx = dmaengine_prep_slave_sg(rspi->ctlr->dma_tx, tx->sgl,
583 desc_tx->callback_param = rspi;
599 disable_irq(other_irq = rspi->tx_irq);
600 if (rx && rspi->rx_irq != other_irq)
601 disable_irq(rspi->rx_irq);
603 rspi_enable_irq(rspi, irq_mask);
604 rspi->dma_callbacked = 0;
608 dma_async_issue_pending(rspi->ctlr->dma_rx);
610 dma_async_issue_pending(rspi->ctlr->dma_tx);
612 ret = wait_event_interruptible_timeout(rspi->wait,
613 rspi->dma_callbacked, HZ);
614 if (ret > 0 && rspi->dma_callbacked) {
617 dmaengine_synchronize(rspi->ctlr->dma_tx);
619 dmaengine_synchronize(rspi->ctlr->dma_rx);
622 dev_err(&rspi->ctlr->dev, "DMA timeout\n");
626 dmaengine_terminate_sync(rspi->ctlr->dma_tx);
628 dmaengine_terminate_sync(rspi->ctlr->dma_rx);
631 rspi_disable_irq(rspi, irq_mask);
634 enable_irq(rspi->tx_irq);
635 if (rx && rspi->rx_irq != other_irq)
636 enable_irq(rspi->rx_irq);
642 dmaengine_terminate_sync(rspi->ctlr->dma_rx);
645 dev_warn_once(&rspi->ctlr->dev,
651 static void rspi_receive_init(const struct rspi_data *rspi)
655 spsr = rspi_read8(rspi, RSPI_SPSR);
657 rspi_read_data(rspi); /* dummy read */
659 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
663 static void rspi_rz_receive_init(const struct rspi_data *rspi)
665 rspi_receive_init(rspi);
666 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
667 rspi_write8(rspi, 0, RSPI_SPBFCR);
670 static void qspi_receive_init(const struct rspi_data *rspi)
674 spsr = rspi_read8(rspi, RSPI_SPSR);
676 rspi_read_data(rspi); /* dummy read */
677 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
678 rspi_write8(rspi, 0, QSPI_SPBFCR);
681 static bool __rspi_can_dma(const struct rspi_data *rspi,
684 return xfer->len > rspi->ops->fifo_size;
690 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
692 return __rspi_can_dma(rspi, xfer);
695 static int rspi_dma_check_then_transfer(struct rspi_data *rspi,
698 if (!rspi->ctlr->can_dma || !__rspi_can_dma(rspi, xfer))
702 return rspi_dma_transfer(rspi, &xfer->tx_sg,
706 static int rspi_common_transfer(struct rspi_data *rspi,
711 xfer->effective_speed_hz = rspi->speed_hz;
713 ret = rspi_dma_check_then_transfer(rspi, xfer);
717 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
722 rspi_wait_for_tx_empty(rspi);
730 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
733 spcr = rspi_read8(rspi, RSPI_SPCR);
735 rspi_receive_init(rspi);
740 rspi_write8(rspi, spcr, RSPI_SPCR);
742 return rspi_common_transfer(rspi, xfer);
749 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
751 rspi_rz_receive_init(rspi);
753 return rspi_common_transfer(rspi, xfer);
756 static int qspi_trigger_transfer_out_in(struct rspi_data *rspi, const u8 *tx,
763 n = qspi_set_send_trigger(rspi, len);
764 qspi_set_receive_trigger(rspi, len);
765 ret = rspi_wait_for_tx_empty(rspi);
767 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
771 rspi_write_data(rspi, *tx++);
773 ret = rspi_wait_for_rx_full(rspi);
775 dev_err(&rspi->ctlr->dev, "receive timeout\n");
779 *rx++ = rspi_read_data(rspi);
787 static int qspi_transfer_out_in(struct rspi_data *rspi,
792 qspi_receive_init(rspi);
794 ret = rspi_dma_check_then_transfer(rspi, xfer);
798 return qspi_trigger_transfer_out_in(rspi, xfer->tx_buf,
802 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
809 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
810 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL);
816 len = qspi_set_send_trigger(rspi, n);
817 ret = rspi_wait_for_tx_empty(rspi);
819 dev_err(&rspi->ctlr->dev, "transmit timeout\n");
823 rspi_write_data(rspi, *tx++);
829 rspi_wait_for_tx_empty(rspi);
834 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
841 if (rspi->ctlr->can_dma && __rspi_can_dma(rspi, xfer)) {
842 ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg);
848 len = qspi_set_receive_trigger(rspi, n);
849 ret = rspi_wait_for_rx_full(rspi);
851 dev_err(&rspi->ctlr->dev, "receive timeout\n");
855 *rx++ = rspi_read_data(rspi);
866 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
868 xfer->effective_speed_hz = rspi->speed_hz;
870 return qspi_transfer_out_in(rspi, xfer);
873 return qspi_transfer_out(rspi, xfer);
876 return qspi_transfer_in(rspi, xfer);
879 return qspi_transfer_out_in(rspi, xfer);
907 static int qspi_setup_sequencer(struct rspi_data *rspi,
924 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
934 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
941 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
942 rspi_write8(rspi, i - 1, RSPI_SPSCR);
950 struct rspi_data *rspi = spi_controller_get_devdata(spi->controller);
956 pm_runtime_get_sync(&rspi->pdev->dev);
957 spin_lock_irq(&rspi->lock);
959 sslp = rspi_read8(rspi, RSPI_SSLP);
964 rspi_write8(rspi, sslp, RSPI_SSLP);
966 spin_unlock_irq(&rspi->lock);
967 pm_runtime_put(&rspi->pdev->dev);
974 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
989 rspi->speed_hz = spi->max_speed_hz;
991 if (xfer->speed_hz < rspi->speed_hz)
992 rspi->speed_hz = xfer->speed_hz;
995 rspi->spcmd = SPCMD_SSLKP;
997 rspi->spcmd |= SPCMD_CPOL;
999 rspi->spcmd |= SPCMD_CPHA;
1001 rspi->spcmd |= SPCMD_LSBF;
1004 rspi->spcmd |= SPCMD_SSLA(spi_get_csgpiod(spi, 0) ? rspi->ctlr->unused_native_cs
1008 rspi->sppcr = 0;
1010 rspi->sppcr |= SPPCR_SPLP;
1012 rspi->ops->set_config_register(rspi, 8);
1017 ret = qspi_setup_sequencer(rspi, msg);
1023 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
1030 struct rspi_data *rspi = spi_controller_get_devdata(ctlr);
1033 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
1036 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
1037 rspi_write8(rspi, 0, RSPI_SPSCR);
1043 struct rspi_data *rspi = _sr;
1048 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1056 rspi_disable_irq(rspi, disable_irq);
1057 wake_up(&rspi->wait);
1065 struct rspi_data *rspi = _sr;
1068 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1070 rspi_disable_irq(rspi, SPCR_SPRIE);
1071 wake_up(&rspi->wait);
1080 struct rspi_data *rspi = _sr;
1083 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
1085 rspi_disable_irq(rspi, SPCR_SPTIE);
1086 wake_up(&rspi->wait);
1177 struct rspi_data *rspi = platform_get_drvdata(pdev);
1179 rspi_release_dma(rspi->ctlr);
1217 { .compatible = "renesas,rspi", .data = &rspi_ops },
1219 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1291 struct rspi_data *rspi;
1315 rspi = spi_controller_get_devdata(ctlr);
1316 platform_set_drvdata(pdev, rspi);
1317 rspi->ops = ops;
1318 rspi->ctlr = ctlr;
1320 rspi->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1321 if (IS_ERR(rspi->addr)) {
1322 ret = PTR_ERR(rspi->addr);
1326 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1327 if (IS_ERR(rspi->clk)) {
1329 ret = PTR_ERR(rspi->clk);
1333 rspi->pdev = pdev;
1336 init_waitqueue_head(&rspi->wait);
1337 spin_lock_init(&rspi->lock);
1347 clksrc = clk_get_rate(rspi->clk);
1353 ctlr->max_native_cs = rspi->ops->num_hw_ss;
1361 rspi->rx_irq = rspi->tx_irq = ret;
1363 rspi->rx_irq = ret;
1366 rspi->tx_irq = ret;
1369 if (rspi->rx_irq == rspi->tx_irq) {
1371 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1372 "mux", rspi);
1375 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1376 "rx", rspi);
1378 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1379 rspi_irq_tx, "tx", rspi);
1411 { "rspi", (kernel_ulong_t)&rspi_ops },
1420 struct rspi_data *rspi = dev_get_drvdata(dev);
1422 return spi_controller_suspend(rspi->ctlr);
1427 struct rspi_data *rspi = dev_get_drvdata(dev);
1429 return spi_controller_resume(rspi->ctlr);