Lines Matching refs:ctlr
244 struct spi_controller *ctlr = spi->controller;
245 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
275 static void rockchip_spi_handle_err(struct spi_controller *ctlr,
278 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
290 dmaengine_terminate_async(ctlr->dma_tx);
293 dmaengine_terminate_async(ctlr->dma_rx);
351 struct spi_controller *ctlr = dev_id;
352 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
356 ctlr->target_abort(ctlr);
371 spi_finalize_current_transfer(ctlr);
378 struct spi_controller *ctlr,
404 struct spi_controller *ctlr = data;
405 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
415 spi_finalize_current_transfer(ctlr);
420 struct spi_controller *ctlr = data;
421 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
428 wait_for_tx_idle(rs, ctlr->target);
431 spi_finalize_current_transfer(ctlr);
448 struct spi_controller *ctlr, struct spi_transfer *xfer)
466 dmaengine_slave_config(ctlr->dma_rx, &rxconf);
469 ctlr->dma_rx,
476 rxdesc->callback_param = ctlr;
488 dmaengine_slave_config(ctlr->dma_tx, &txconf);
491 ctlr->dma_tx,
496 dmaengine_terminate_sync(ctlr->dma_rx);
501 txdesc->callback_param = ctlr;
507 ctlr->dma_rx->cookie = dmaengine_submit(rxdesc);
508 dma_async_issue_pending(ctlr->dma_rx);
519 dma_async_issue_pending(ctlr->dma_tx);
570 * ctlr->bits_per_word_mask, so this shouldn't
617 static int rockchip_spi_target_abort(struct spi_controller *ctlr)
619 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
626 dmaengine_pause(ctlr->dma_rx);
627 status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state);
657 dmaengine_terminate_sync(ctlr->dma_rx);
659 dmaengine_terminate_sync(ctlr->dma_tx);
663 spi_finalize_current_transfer(ctlr);
669 struct spi_controller *ctlr,
673 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
679 spi_finalize_current_transfer(ctlr);
698 use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false;
700 ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->target);
705 return rockchip_spi_prepare_dma(rs, ctlr, xfer);
707 return rockchip_spi_prepare_irq(rs, ctlr, xfer);
710 static bool rockchip_spi_can_dma(struct spi_controller *ctlr,
714 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
756 struct spi_controller *ctlr;
765 ctlr = spi_alloc_target(&pdev->dev,
768 ctlr = spi_alloc_host(&pdev->dev,
771 if (!ctlr)
774 platform_set_drvdata(pdev, ctlr);
776 rs = spi_controller_get_devdata(ctlr);
818 IRQF_ONESHOT, dev_name(&pdev->dev), ctlr);
854 ctlr->auto_runtime_pm = true;
855 ctlr->bus_num = pdev->id;
856 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST;
858 ctlr->mode_bits |= SPI_NO_CS;
859 ctlr->target_abort = rockchip_spi_target_abort;
861 ctlr->flags = SPI_CONTROLLER_GPIO_SS;
862 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM;
869 ctlr->num_chipselect = num_cs;
870 ctlr->use_gpio_descriptors = true;
872 ctlr->dev.of_node = pdev->dev.of_node;
873 ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4);
874 ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX;
875 ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT);
877 ctlr->setup = rockchip_spi_setup;
878 ctlr->set_cs = rockchip_spi_set_cs;
879 ctlr->transfer_one = rockchip_spi_transfer_one;
880 ctlr->max_transfer_size = rockchip_spi_max_transfer_size;
881 ctlr->handle_err = rockchip_spi_handle_err;
883 ctlr->dma_tx = dma_request_chan(rs->dev, "tx");
884 if (IS_ERR(ctlr->dma_tx)) {
886 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) {
891 ctlr->dma_tx = NULL;
894 ctlr->dma_rx = dma_request_chan(rs->dev, "rx");
895 if (IS_ERR(ctlr->dma_rx)) {
896 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) {
901 ctlr->dma_rx = NULL;
904 if (ctlr->dma_tx && ctlr->dma_rx) {
907 ctlr->can_dma = rockchip_spi_can_dma;
913 ctlr->mode_bits |= SPI_CS_HIGH;
914 if (ctlr->can_dma && target_mode)
924 ret = devm_spi_register_controller(&pdev->dev, ctlr);
933 if (ctlr->dma_rx)
934 dma_release_channel(ctlr->dma_rx);
936 if (ctlr->dma_tx)
937 dma_release_channel(ctlr->dma_tx);
945 spi_controller_put(ctlr);
952 struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev));
953 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
964 if (ctlr->dma_tx)
965 dma_release_channel(ctlr->dma_tx);
966 if (ctlr->dma_rx)
967 dma_release_channel(ctlr->dma_rx);
969 spi_controller_put(ctlr);
976 struct spi_controller *ctlr = dev_get_drvdata(dev);
977 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
979 ret = spi_controller_suspend(ctlr);
994 struct spi_controller *ctlr = dev_get_drvdata(dev);
995 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1007 ret = spi_controller_resume(ctlr);
1020 struct spi_controller *ctlr = dev_get_drvdata(dev);
1021 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
1032 struct spi_controller *ctlr = dev_get_drvdata(dev);
1033 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);