Lines Matching refs:controller
155 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag)
157 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL);
171 static inline unsigned int spi_qup_len(struct spi_qup *controller)
173 return controller->n_words * controller->w_size;
176 static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
178 u32 opstate = readl_relaxed(controller->base + QUP_STATE);
183 static int spi_qup_set_state(struct spi_qup *controller, u32 state)
189 while (!spi_qup_is_valid_state(controller)) {
198 dev_dbg(controller->dev, "invalid state for %ld,us %d\n",
201 cur_state = readl_relaxed(controller->base + QUP_STATE);
208 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
209 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
213 writel_relaxed(cur_state, controller->base + QUP_STATE);
217 while (!spi_qup_is_valid_state(controller)) {
228 static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words)
230 u8 *rx_buf = controller->rx_buf;
236 word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
238 num_bytes = min_t(int, spi_qup_len(controller) -
239 controller->rx_bytes,
240 controller->w_size);
243 controller->rx_bytes += num_bytes;
247 for (i = 0; i < num_bytes; i++, controller->rx_bytes++) {
255 shift *= (controller->w_size - i - 1);
256 rx_buf[controller->rx_bytes] = word >> shift;
261 static void spi_qup_read(struct spi_qup *controller, u32 *opflags)
264 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
266 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes,
267 controller->w_size);
268 words_per_block = controller->in_blk_sz >> 2;
273 controller->base + QUP_OPERATIONAL);
282 if (!spi_qup_is_flag_set(controller,
290 spi_qup_read_from_fifo(controller, num_words);
295 if (is_block_mode && !spi_qup_is_flag_set(controller,
309 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
312 controller->base + QUP_OPERATIONAL);
316 static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words)
318 const u8 *tx_buf = controller->tx_buf;
325 num_bytes = min_t(int, spi_qup_len(controller) -
326 controller->tx_bytes,
327 controller->w_size);
330 data = tx_buf[controller->tx_bytes + i];
334 controller->tx_bytes += num_bytes;
336 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
347 static void spi_qup_write(struct spi_qup *controller)
349 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK;
352 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes,
353 controller->w_size);
354 words_per_block = controller->out_blk_sz >> 2;
359 controller->base + QUP_OPERATIONAL);
369 if (spi_qup_is_flag_set(controller,
376 spi_qup_write_to_fifo(controller, num_words);
381 if (is_block_mode && !spi_qup_is_flag_set(controller,
448 struct spi_controller *host = spi->controller;
516 struct spi_controller *host = spi->controller;
578 static bool spi_qup_data_pending(struct spi_qup *controller)
582 remainder_tx = DIV_ROUND_UP(spi_qup_len(controller) -
583 controller->tx_bytes, controller->w_size);
585 remainder_rx = DIV_ROUND_UP(spi_qup_len(controller) -
586 controller->rx_bytes, controller->w_size);
593 struct spi_qup *controller = dev_id;
597 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
598 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
599 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
601 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
602 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
606 dev_warn(controller->dev, "OUTPUT_OVER_RUN\n");
608 dev_warn(controller->dev, "INPUT_UNDER_RUN\n");
610 dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n");
612 dev_warn(controller->dev, "INPUT_OVER_RUN\n");
619 dev_warn(controller->dev, "CLK_OVER_RUN\n");
621 dev_warn(controller->dev, "CLK_UNDER_RUN\n");
626 spin_lock(&controller->lock);
627 if (!controller->error)
628 controller->error = error;
629 spin_unlock(&controller->lock);
631 if (spi_qup_is_dma_xfer(controller->mode)) {
632 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
635 spi_qup_read(controller, &opflags);
638 spi_qup_write(controller);
640 if (!spi_qup_data_pending(controller))
641 complete(&controller->done);
645 complete(&controller->done);
648 if (!spi_qup_is_dma_xfer(controller->mode)) {
649 if (spi_qup_data_pending(controller))
652 complete(&controller->done);
661 struct spi_qup *controller = spi_controller_get_devdata(spi->controller);
664 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
665 dev_err(controller->dev, "too big size for loopback %d > %d\n",
666 xfer->len, controller->in_fifo_sz);
670 ret = clk_set_rate(controller->cclk, xfer->speed_hz);
672 dev_err(controller->dev, "fail to set frequency %d",
677 controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8);
678 controller->n_words = xfer->len / controller->w_size;
680 if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32)))
681 controller->mode = QUP_IO_M_MODE_FIFO;
682 else if (spi->controller->can_dma &&
683 spi->controller->can_dma(spi->controller, spi, xfer) &&
684 spi->controller->cur_msg_mapped)
685 controller->mode = QUP_IO_M_MODE_BAM;
687 controller->mode = QUP_IO_M_MODE_BLOCK;
695 struct spi_qup *controller = spi_controller_get_devdata(spi->controller);
699 spin_lock_irqsave(&controller->lock, flags);
700 controller->xfer = xfer;
701 controller->error = 0;
702 controller->rx_bytes = 0;
703 controller->tx_bytes = 0;
704 spin_unlock_irqrestore(&controller->lock, flags);
707 if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
708 dev_err(controller->dev, "cannot set RESET state\n");
712 switch (controller->mode) {
714 writel_relaxed(controller->n_words,
715 controller->base + QUP_MX_READ_CNT);
716 writel_relaxed(controller->n_words,
717 controller->base + QUP_MX_WRITE_CNT);
719 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
720 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
723 writel_relaxed(controller->n_words,
724 controller->base + QUP_MX_INPUT_CNT);
725 writel_relaxed(controller->n_words,
726 controller->base + QUP_MX_OUTPUT_CNT);
728 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
729 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
731 if (!controller->qup_v1) {
734 input_cnt = controller->base + QUP_MX_INPUT_CNT;
744 writel_relaxed(controller->n_words, input_cnt);
746 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
750 reinit_completion(&controller->done);
751 writel_relaxed(controller->n_words,
752 controller->base + QUP_MX_INPUT_CNT);
753 writel_relaxed(controller->n_words,
754 controller->base + QUP_MX_OUTPUT_CNT);
756 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
757 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
760 dev_err(controller->dev, "unknown mode = %d\n",
761 controller->mode);
765 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
769 if (!spi_qup_is_dma_xfer(controller->mode))
774 iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
775 iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
777 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
779 control = readl_relaxed(controller->base + SPI_IO_CONTROL);
786 writel_relaxed(control, controller->base + SPI_IO_CONTROL);
788 config = readl_relaxed(controller->base + SPI_CONFIG);
809 writel_relaxed(config, controller->base + SPI_CONFIG);
811 config = readl_relaxed(controller->base + QUP_CONFIG);
816 if (spi_qup_is_dma_xfer(controller->mode)) {
823 writel_relaxed(config, controller->base + QUP_CONFIG);
826 if (!controller->qup_v1) {
834 if (spi_qup_is_dma_xfer(controller->mode))
837 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
847 struct spi_qup *controller = spi_controller_get_devdata(host);
860 reinit_completion(&controller->done);
862 spin_lock_irqsave(&controller->lock, flags);
863 controller->xfer = xfer;
864 controller->error = 0;
865 controller->rx_bytes = 0;
866 controller->tx_bytes = 0;
867 spin_unlock_irqrestore(&controller->lock, flags);
869 if (spi_qup_is_dma_xfer(controller->mode))
874 spi_qup_set_state(controller, QUP_STATE_RESET);
875 spin_lock_irqsave(&controller->lock, flags);
877 ret = controller->error;
878 spin_unlock_irqrestore(&controller->lock, flags);
880 if (ret && spi_qup_is_dma_xfer(controller->mode))
977 struct spi_qup *controller;
981 controller = spi_controller_get_devdata(spi->controller);
982 spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL);
990 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL);
997 struct spi_qup *controller;
1057 controller = spi_controller_get_devdata(host);
1059 controller->dev = dev;
1060 controller->base = base;
1061 controller->iclk = iclk;
1062 controller->cclk = cclk;
1063 controller->irq = irq;
1071 controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev);
1073 if (!controller->qup_v1)
1076 spin_lock_init(&controller->lock);
1077 init_completion(&controller->done);
1096 controller->out_blk_sz = size * 16;
1098 controller->out_blk_sz = 4;
1102 controller->in_blk_sz = size * 16;
1104 controller->in_blk_sz = 4;
1107 controller->out_fifo_sz = controller->out_blk_sz * (2 << size);
1110 controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
1113 controller->in_blk_sz, controller->in_fifo_sz,
1114 controller->out_blk_sz, controller->out_fifo_sz);
1118 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1127 if (!controller->qup_v1)
1134 if (controller->qup_v1)
1143 IRQF_TRIGGER_HIGH, pdev->name, controller);
1174 struct spi_qup *controller = spi_controller_get_devdata(host);
1178 config = readl(controller->base + QUP_CONFIG);
1180 writel_relaxed(config, controller->base + QUP_CONFIG);
1182 clk_disable_unprepare(controller->cclk);
1183 clk_disable_unprepare(controller->iclk);
1191 struct spi_qup *controller = spi_controller_get_devdata(host);
1195 ret = clk_prepare_enable(controller->iclk);
1199 ret = clk_prepare_enable(controller->cclk);
1201 clk_disable_unprepare(controller->iclk);
1206 config = readl_relaxed(controller->base + QUP_CONFIG);
1208 writel_relaxed(config, controller->base + QUP_CONFIG);
1217 struct spi_qup *controller = spi_controller_get_devdata(host);
1229 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1233 clk_disable_unprepare(controller->cclk);
1234 clk_disable_unprepare(controller->iclk);
1241 struct spi_qup *controller = spi_controller_get_devdata(host);
1244 ret = clk_prepare_enable(controller->iclk);
1248 ret = clk_prepare_enable(controller->cclk);
1250 clk_disable_unprepare(controller->iclk);
1254 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1265 clk_disable_unprepare(controller->cclk);
1266 clk_disable_unprepare(controller->iclk);
1274 struct spi_qup *controller = spi_controller_get_devdata(host);
1280 ret = spi_qup_set_state(controller, QUP_STATE_RESET);
1282 dev_warn(&pdev->dev, "failed to reset controller (%pe)\n",
1285 clk_disable_unprepare(controller->cclk);
1286 clk_disable_unprepare(controller->iclk);