Lines Matching refs:base
125 void __iomem *base;
157 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL);
178 u32 opstate = readl_relaxed(controller->base + QUP_STATE);
201 cur_state = readl_relaxed(controller->base + QUP_STATE);
208 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
209 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE);
213 writel_relaxed(cur_state, controller->base + QUP_STATE);
236 word = readl_relaxed(controller->base + QUP_INPUT_FIFO);
273 controller->base + QUP_OPERATIONAL);
309 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
312 controller->base + QUP_OPERATIONAL);
336 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO);
359 controller->base + QUP_OPERATIONAL);
597 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS);
598 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS);
599 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL);
601 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS);
602 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS);
632 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL);
715 controller->base + QUP_MX_READ_CNT);
717 controller->base + QUP_MX_WRITE_CNT);
719 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
720 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
724 controller->base + QUP_MX_INPUT_CNT);
726 controller->base + QUP_MX_OUTPUT_CNT);
728 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
729 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
734 input_cnt = controller->base + QUP_MX_INPUT_CNT;
746 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
752 controller->base + QUP_MX_INPUT_CNT);
754 controller->base + QUP_MX_OUTPUT_CNT);
756 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
757 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
765 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
777 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
779 control = readl_relaxed(controller->base + SPI_IO_CONTROL);
786 writel_relaxed(control, controller->base + SPI_IO_CONTROL);
788 config = readl_relaxed(controller->base + SPI_CONFIG);
809 writel_relaxed(config, controller->base + SPI_CONFIG);
811 config = readl_relaxed(controller->base + QUP_CONFIG);
823 writel_relaxed(config, controller->base + QUP_CONFIG);
837 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
924 static int spi_qup_init_dma(struct spi_controller *host, resource_size_t base)
946 rx_conf->src_addr = base + QUP_INPUT_FIFO;
951 tx_conf->dst_addr = base + QUP_OUTPUT_FIFO;
982 spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL);
990 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL);
1000 void __iomem *base;
1005 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1006 if (IS_ERR(base))
1007 return PTR_ERR(base);
1060 controller->base = base;
1092 iomode = readl_relaxed(base + QUP_IO_M_MODES);
1116 writel_relaxed(1, base + QUP_SW_RESET);
1124 writel_relaxed(0, base + QUP_OPERATIONAL);
1125 writel_relaxed(0, base + QUP_IO_M_MODES);
1128 writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
1131 base + SPI_ERROR_FLAGS_EN);
1137 base + QUP_ERROR_FLAGS_EN);
1139 writel_relaxed(0, base + SPI_CONFIG);
1140 writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
1178 config = readl(controller->base + QUP_CONFIG);
1180 writel_relaxed(config, controller->base + QUP_CONFIG);
1206 config = readl_relaxed(controller->base + QUP_CONFIG);
1208 writel_relaxed(config, controller->base + QUP_CONFIG);