Lines Matching refs:ctrl
182 static u32 qspi_buswidth_to_iomode(struct qcom_qspi *ctrl,
193 dev_warn_once(ctrl->dev,
199 static void qcom_qspi_pio_xfer_cfg(struct qcom_qspi *ctrl)
205 xfer = &ctrl->xfer;
206 pio_xfer_cfg = readl(ctrl->base + PIO_XFER_CFG);
214 iomode = qspi_buswidth_to_iomode(ctrl, xfer->buswidth);
217 writel(pio_xfer_cfg, ctrl->base + PIO_XFER_CFG);
220 static void qcom_qspi_pio_xfer_ctrl(struct qcom_qspi *ctrl)
224 pio_xfer_ctrl = readl(ctrl->base + PIO_XFER_CTRL);
226 pio_xfer_ctrl |= ctrl->xfer.rem_bytes;
227 writel(pio_xfer_ctrl, ctrl->base + PIO_XFER_CTRL);
230 static void qcom_qspi_pio_xfer(struct qcom_qspi *ctrl)
234 qcom_qspi_pio_xfer_cfg(ctrl);
237 writel(QSPI_ALL_IRQS, ctrl->base + MSTR_INT_STATUS);
240 if (ctrl->xfer.dir == QSPI_WRITE)
244 writel(ints, ctrl->base + MSTR_INT_EN);
247 qcom_qspi_pio_xfer_ctrl(ctrl);
254 struct qcom_qspi *ctrl = spi_controller_get_devdata(host);
258 spin_lock_irqsave(&ctrl->lock, flags);
259 writel(0, ctrl->base + MSTR_INT_EN);
260 int_status = readl(ctrl->base + MSTR_INT_STATUS);
261 writel(int_status, ctrl->base + MSTR_INT_STATUS);
262 ctrl->xfer.rem_bytes = 0;
265 for (i = 0; i < ctrl->n_cmd_desc; i++)
266 dma_pool_free(ctrl->dma_cmd_pool, ctrl->virt_cmd_desc[i],
267 ctrl->dma_cmd_desc[i]);
268 ctrl->n_cmd_desc = 0;
269 spin_unlock_irqrestore(&ctrl->lock, flags);
272 static int qcom_qspi_set_speed(struct qcom_qspi *ctrl, unsigned long speed_hz)
277 if (speed_hz == ctrl->last_speed)
281 ret = dev_pm_opp_set_rate(ctrl->dev, speed_hz * 4);
283 dev_err(ctrl->dev, "Failed to set core clk %d\n", ret);
292 ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, avg_bw_cpu, avg_bw_cpu);
294 dev_err(ctrl->dev, "%s: ICC BW voting failed for cpu: %d\n",
299 ctrl->last_speed = speed_hz;
304 static int qcom_qspi_alloc_desc(struct qcom_qspi *ctrl, dma_addr_t dma_ptr,
311 virt_cmd_desc = dma_pool_alloc(ctrl->dma_cmd_pool, GFP_ATOMIC | __GFP_ZERO, &dma_cmd_desc);
313 dev_warn_once(ctrl->dev, "Couldn't find memory for descriptor\n");
317 ctrl->virt_cmd_desc[ctrl->n_cmd_desc] = virt_cmd_desc;
318 ctrl->dma_cmd_desc[ctrl->n_cmd_desc] = dma_cmd_desc;
319 ctrl->n_cmd_desc++;
323 virt_cmd_desc->direction = ctrl->xfer.dir;
324 virt_cmd_desc->multi_io_mode = qspi_buswidth_to_iomode(ctrl, ctrl->xfer.buswidth);
325 virt_cmd_desc->fragment = !ctrl->xfer.is_last;
329 if (ctrl->n_cmd_desc >= 2) {
330 prev = (ctrl->virt_cmd_desc)[ctrl->n_cmd_desc - 2];
338 static int qcom_qspi_setup_dma_desc(struct qcom_qspi *ctrl,
347 if (ctrl->n_cmd_desc) {
348 dev_err(ctrl->dev, "Remnant dma buffers n_cmd_desc-%d\n", ctrl->n_cmd_desc);
352 sgt = (ctrl->xfer.dir == QSPI_READ) ? &xfer->rx_sg : &xfer->tx_sg;
354 dev_warn_once(ctrl->dev, "Cannot handle %d entries in scatter list\n", sgt->nents);
362 dev_warn_once(ctrl->dev, "dma_address not aligned to %d\n", QSPI_ALIGN_REQ);
371 if (ctrl->xfer.dir == QSPI_READ && (dma_len_sg & 0x03)) {
372 dev_warn_once(ctrl->dev, "fallback to PIO for read of size %#010x\n",
382 ret = qcom_qspi_alloc_desc(ctrl, dma_ptr_sg, dma_len_sg);
389 for (i = 0; i < ctrl->n_cmd_desc; i++)
390 dma_pool_free(ctrl->dma_cmd_pool, ctrl->virt_cmd_desc[i],
391 ctrl->dma_cmd_desc[i]);
392 ctrl->n_cmd_desc = 0;
396 static void qcom_qspi_dma_xfer(struct qcom_qspi *ctrl)
399 writel(DMA_CHAIN_DONE, ctrl->base + MSTR_INT_EN);
402 writel((u32)((ctrl->dma_cmd_desc)[0]), ctrl->base + NEXT_DMA_DESC_ADDR);
418 struct qcom_qspi *ctrl = spi_controller_get_devdata(host);
428 ret = qcom_qspi_set_speed(ctrl, speed_hz);
432 spin_lock_irqsave(&ctrl->lock, flags);
433 mstr_cfg = readl(ctrl->base + MSTR_CONFIG);
437 ctrl->xfer.dir = QSPI_READ;
438 ctrl->xfer.buswidth = xfer->rx_nbits;
439 ctrl->xfer.rx_buf = xfer->rx_buf;
441 ctrl->xfer.dir = QSPI_WRITE;
442 ctrl->xfer.buswidth = xfer->tx_nbits;
443 ctrl->xfer.tx_buf = xfer->tx_buf;
445 ctrl->xfer.is_last = list_is_last(&xfer->transfer_list,
447 ctrl->xfer.rem_bytes = xfer->len;
453 writel(mstr_cfg, ctrl->base + MSTR_CONFIG);
456 ret = qcom_qspi_setup_dma_desc(ctrl, xfer);
460 qcom_qspi_dma_xfer(ctrl);
464 dev_warn_once(ctrl->dev, "DMA failure, falling back to PIO\n");
470 writel(mstr_cfg, ctrl->base + MSTR_CONFIG);
472 qcom_qspi_pio_xfer(ctrl);
475 spin_unlock_irqrestore(&ctrl->lock, flags);
488 struct qcom_qspi *ctrl;
493 ctrl = spi_controller_get_devdata(host);
494 spin_lock_irqsave(&ctrl->lock, flags);
496 mstr_cfg = readl(ctrl->base + MSTR_CONFIG);
508 writel(mstr_cfg, ctrl->base + MSTR_CONFIG);
509 spin_unlock_irqrestore(&ctrl->lock, flags);
514 static int qcom_qspi_alloc_dma(struct qcom_qspi *ctrl)
516 ctrl->dma_cmd_pool = dmam_pool_create("qspi cmd desc pool",
517 ctrl->dev, sizeof(struct qspi_cmd_desc), 0, 0);
518 if (!ctrl->dma_cmd_pool)
524 static irqreturn_t pio_read(struct qcom_qspi *ctrl)
535 rd_fifo_status = readl(ctrl->base + RD_FIFO_STATUS);
538 dev_dbg(ctrl->dev, "Spurious IRQ %#x\n", rd_fifo_status);
543 wr_cnts = min(wr_cnts, ctrl->xfer.rem_bytes);
549 word_buf = ctrl->xfer.rx_buf;
550 ctrl->xfer.rem_bytes -= words_to_read * QSPI_BYTES_PER_WORD;
551 ioread32_rep(ctrl->base + RD_FIFO, word_buf, words_to_read);
552 ctrl->xfer.rx_buf = word_buf + words_to_read;
556 byte_buf = ctrl->xfer.rx_buf;
557 rd_fifo = readl(ctrl->base + RD_FIFO);
558 ctrl->xfer.rem_bytes -= bytes_to_read;
561 ctrl->xfer.rx_buf = byte_buf;
567 static irqreturn_t pio_write(struct qcom_qspi *ctrl)
569 const void *xfer_buf = ctrl->xfer.tx_buf;
577 wr_fifo_bytes = readl(ctrl->base + PIO_XFER_STATUS);
580 if (ctrl->xfer.rem_bytes < QSPI_BYTES_PER_WORD) {
582 wr_size = min(wr_fifo_bytes, ctrl->xfer.rem_bytes);
583 ctrl->xfer.rem_bytes -= wr_size;
588 ctrl->base + PIO_DATAOUT_1B);
589 ctrl->xfer.tx_buf = byte_buf;
596 rem_words = ctrl->xfer.rem_bytes / QSPI_BYTES_PER_WORD;
600 ctrl->xfer.rem_bytes -= wr_size * QSPI_BYTES_PER_WORD;
603 iowrite32_rep(ctrl->base + PIO_DATAOUT_4B, word_buf, wr_size);
604 ctrl->xfer.tx_buf = word_buf + wr_size;
614 struct qcom_qspi *ctrl = dev_id;
617 spin_lock(&ctrl->lock);
619 int_status = readl(ctrl->base + MSTR_INT_STATUS);
620 writel(int_status, ctrl->base + MSTR_INT_STATUS);
623 int_status &= readl(ctrl->base + MSTR_INT_EN);
626 if (ctrl->xfer.dir == QSPI_WRITE) {
628 ret = pio_write(ctrl);
631 ret = pio_read(ctrl);
636 dev_err(ctrl->dev, "IRQ error: FIFO underrun\n");
638 dev_err(ctrl->dev, "IRQ error: FIFO overrun\n");
640 dev_err(ctrl->dev, "IRQ error: NOC response error\n");
644 if (!ctrl->xfer.rem_bytes) {
645 writel(0, ctrl->base + MSTR_INT_EN);
646 spi_finalize_current_transfer(dev_get_drvdata(ctrl->dev));
653 writel(0, ctrl->base + MSTR_INT_EN);
654 ctrl->xfer.rem_bytes = 0;
656 for (i = 0; i < ctrl->n_cmd_desc; i++)
657 dma_pool_free(ctrl->dma_cmd_pool, ctrl->virt_cmd_desc[i],
658 ctrl->dma_cmd_desc[i]);
659 ctrl->n_cmd_desc = 0;
662 spi_finalize_current_transfer(dev_get_drvdata(ctrl->dev));
665 spin_unlock(&ctrl->lock);
698 struct qcom_qspi *ctrl;
702 host = devm_spi_alloc_host(dev, sizeof(*ctrl));
708 ctrl = spi_controller_get_devdata(host);
710 spin_lock_init(&ctrl->lock);
711 ctrl->dev = dev;
712 ctrl->base = devm_platform_ioremap_resource(pdev, 0);
713 if (IS_ERR(ctrl->base))
714 return PTR_ERR(ctrl->base);
716 ctrl->clks = devm_kcalloc(dev, QSPI_NUM_CLKS,
717 sizeof(*ctrl->clks), GFP_KERNEL);
718 if (!ctrl->clks)
721 ctrl->clks[QSPI_CLK_CORE].id = "core";
722 ctrl->clks[QSPI_CLK_IFACE].id = "iface";
723 ret = devm_clk_bulk_get(dev, QSPI_NUM_CLKS, ctrl->clks);
727 ctrl->icc_path_cpu_to_qspi = devm_of_icc_get(dev, "qspi-config");
728 if (IS_ERR(ctrl->icc_path_cpu_to_qspi))
729 return dev_err_probe(dev, PTR_ERR(ctrl->icc_path_cpu_to_qspi),
733 ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, Bps_to_icc(1000),
736 dev_err(ctrl->dev, "%s: ICC BW voting failed for cpu: %d\n",
741 ret = icc_disable(ctrl->icc_path_cpu_to_qspi);
743 dev_err(ctrl->dev, "%s: ICC disable failed for cpu: %d\n",
751 ret = devm_request_irq(dev, ret, qcom_qspi_irq, 0, dev_name(dev), ctrl);
789 ret = qcom_qspi_alloc_dma(ctrl);
819 struct qcom_qspi *ctrl = spi_controller_get_devdata(host);
824 clk_bulk_disable_unprepare(QSPI_NUM_CLKS, ctrl->clks);
826 ret = icc_disable(ctrl->icc_path_cpu_to_qspi);
828 dev_err_ratelimited(ctrl->dev, "%s: ICC disable failed for cpu: %d\n",
841 struct qcom_qspi *ctrl = spi_controller_get_devdata(host);
846 ret = icc_enable(ctrl->icc_path_cpu_to_qspi);
848 dev_err_ratelimited(ctrl->dev, "%s: ICC enable failed for cpu: %d\n",
853 ret = clk_bulk_prepare_enable(QSPI_NUM_CLKS, ctrl->clks);
857 return dev_pm_opp_set_rate(dev, ctrl->last_speed * 4);