Lines Matching refs:sccr1_reg
257 u32 *sccr1_reg)
272 *sccr1_reg &= ~mask;
276 u32 *sccr1_reg, u32 threshold)
280 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
283 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold);
286 *sccr1_reg |= SSCR1_RxTresh(threshold);
679 u32 sccr1_reg;
681 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
682 sccr1_reg &= ~SSCR1_TIE;
691 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
707 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
709 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
727 u32 sccr1_reg;
750 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
753 if (!(sccr1_reg & SSCR1_TIE))
757 if (!(sccr1_reg & SSCR1_TINTE))
763 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
764 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);