Lines Matching defs:value
206 static void pxa2xx_spi_update(const struct driver_data *drv_data, u32 reg, u32 mask, u32 value)
208 if ((pxa2xx_spi_read(drv_data, reg) & mask) != value)
209 pxa2xx_spi_write(drv_data, reg, value & mask);
318 unsigned offset, u32 value)
321 writel(value, drv_data->lpss_base + offset);
334 u32 value;
340 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
341 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
342 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
343 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
350 value = __lpss_ssp_read_priv(drv_data,
352 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
354 config->reg_general, value);
364 u32 value, cs;
369 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
373 if (cs != (value & config->cs_sel_mask)) {
381 value &= ~config->cs_sel_mask;
382 value |= cs;
384 config->reg_cs_ctrl, value);
395 u32 value;
402 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
404 value &= ~LPSS_CS_CONTROL_CS_HIGH;
406 value |= LPSS_CS_CONTROL_CS_HIGH;
407 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
418 value = (clkgate & ~LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK) |
421 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
779 * There are formulas to get baud rate value for given input frequency and
802 * In all cases the lowest possible value is better.
822 /* Set initial value for DDS_CLK_RATE */
1349 u32 value;
1351 status = device_property_read_u32(dev, "intel,spi-pxa2xx-type", &value);
1355 type = (enum pxa_ssp_type)value;