Lines Matching defs:drv_data
78 /* LPSS offset from drv_data->ioaddr */
80 /* Register offsets from drv_data->lpss_base or -1 */
171 *lpss_get_config(const struct driver_data *drv_data)
173 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
176 static bool is_lpss_ssp(const struct driver_data *drv_data)
178 switch (drv_data->ssp_type) {
191 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
193 return drv_data->ssp_type == QUARK_X1000_SSP;
196 static bool is_mmp2_ssp(const struct driver_data *drv_data)
198 return drv_data->ssp_type == MMP2_SSP;
201 static bool is_mrfld_ssp(const struct driver_data *drv_data)
203 return drv_data->ssp_type == MRFLD_SSP;
206 static void pxa2xx_spi_update(const struct driver_data *drv_data, u32 reg, u32 mask, u32 value)
208 if ((pxa2xx_spi_read(drv_data, reg) & mask) != value)
209 pxa2xx_spi_write(drv_data, reg, value & mask);
212 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
214 switch (drv_data->ssp_type) {
225 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
227 switch (drv_data->ssp_type) {
237 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
241 switch (drv_data->ssp_type) {
253 return read_SSSR_bits(drv_data, mask) == mask;
256 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
261 switch (drv_data->ssp_type) {
275 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
278 switch (drv_data->ssp_type) {
291 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
294 switch (drv_data->ssp_type) {
311 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
313 WARN_ON(!drv_data->lpss_base);
314 return readl(drv_data->lpss_base + offset);
317 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
320 WARN_ON(!drv_data->lpss_base);
321 writel(value, drv_data->lpss_base + offset);
326 * @drv_data: pointer to the driver private data
331 static void lpss_ssp_setup(struct driver_data *drv_data)
336 config = lpss_get_config(drv_data);
337 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset;
340 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
343 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
346 if (drv_data->controller_info->enable_dma) {
347 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
350 value = __lpss_ssp_read_priv(drv_data,
353 __lpss_ssp_write_priv(drv_data,
362 struct driver_data *drv_data =
369 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
383 __lpss_ssp_write_priv(drv_data,
386 (drv_data->controller->max_speed_hz / 2));
392 struct driver_data *drv_data =
397 config = lpss_get_config(drv_data);
402 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
407 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
417 clkgate = __lpss_ssp_read_priv(drv_data, LPSS_PRIV_CLOCK_GATE);
421 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, value);
422 __lpss_ssp_write_priv(drv_data, LPSS_PRIV_CLOCK_GATE, clkgate);
428 struct driver_data *drv_data =
431 if (drv_data->ssp_type == CE4100_SSP) {
432 pxa2xx_spi_write(drv_data, SSSR, spi_get_chipselect(spi, 0));
436 if (is_lpss_ssp(drv_data))
442 struct driver_data *drv_data =
446 if (drv_data->ssp_type == CE4100_SSP)
451 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
455 if (is_lpss_ssp(drv_data))
467 int pxa2xx_spi_flush(struct driver_data *drv_data)
472 while (read_SSSR_bits(drv_data, SSSR_RNE))
473 pxa2xx_spi_read(drv_data, SSDR);
474 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
475 write_SSSR_CS(drv_data, SSSR_ROR);
480 static void pxa2xx_spi_off(struct driver_data *drv_data)
483 if (is_mmp2_ssp(drv_data))
486 pxa_ssp_disable(drv_data->ssp);
489 static int null_writer(struct driver_data *drv_data)
491 u8 n_bytes = drv_data->n_bytes;
493 if (pxa2xx_spi_txfifo_full(drv_data)
494 || (drv_data->tx == drv_data->tx_end))
497 pxa2xx_spi_write(drv_data, SSDR, 0);
498 drv_data->tx += n_bytes;
503 static int null_reader(struct driver_data *drv_data)
505 u8 n_bytes = drv_data->n_bytes;
507 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
508 pxa2xx_spi_read(drv_data, SSDR);
509 drv_data->rx += n_bytes;
512 return drv_data->rx == drv_data->rx_end;
515 static int u8_writer(struct driver_data *drv_data)
517 if (pxa2xx_spi_txfifo_full(drv_data)
518 || (drv_data->tx == drv_data->tx_end))
521 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
522 ++drv_data->tx;
527 static int u8_reader(struct driver_data *drv_data)
529 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
530 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
531 ++drv_data->rx;
534 return drv_data->rx == drv_data->rx_end;
537 static int u16_writer(struct driver_data *drv_data)
539 if (pxa2xx_spi_txfifo_full(drv_data)
540 || (drv_data->tx == drv_data->tx_end))
543 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
544 drv_data->tx += 2;
549 static int u16_reader(struct driver_data *drv_data)
551 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
552 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
553 drv_data->rx += 2;
556 return drv_data->rx == drv_data->rx_end;
559 static int u32_writer(struct driver_data *drv_data)
561 if (pxa2xx_spi_txfifo_full(drv_data)
562 || (drv_data->tx == drv_data->tx_end))
565 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
566 drv_data->tx += 4;
571 static int u32_reader(struct driver_data *drv_data)
573 while (read_SSSR_bits(drv_data, SSSR_RNE) && drv_data->rx < drv_data->rx_end) {
574 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
575 drv_data->rx += 4;
578 return drv_data->rx == drv_data->rx_end;
581 static void reset_sccr1(struct driver_data *drv_data)
583 u32 mask = drv_data->int_cr1 | drv_data->dma_cr1, threshold;
586 if (drv_data->controller->cur_msg) {
587 chip = spi_get_ctldata(drv_data->controller->cur_msg->spi);
593 switch (drv_data->ssp_type) {
605 pxa2xx_spi_update(drv_data, SSCR1, mask, threshold);
608 static void int_stop_and_reset(struct driver_data *drv_data)
611 write_SSSR_CS(drv_data, drv_data->clear_sr);
612 reset_sccr1(drv_data);
613 if (pxa25x_ssp_comp(drv_data))
616 pxa2xx_spi_write(drv_data, SSTO, 0);
619 static void int_error_stop(struct driver_data *drv_data, const char *msg, int err)
621 int_stop_and_reset(drv_data);
622 pxa2xx_spi_flush(drv_data);
623 pxa2xx_spi_off(drv_data);
625 dev_err(drv_data->ssp->dev, "%s\n", msg);
627 drv_data->controller->cur_msg->status = err;
628 spi_finalize_current_transfer(drv_data->controller);
631 static void int_transfer_complete(struct driver_data *drv_data)
633 int_stop_and_reset(drv_data);
635 spi_finalize_current_transfer(drv_data->controller);
638 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
642 irq_status = read_SSSR_bits(drv_data, drv_data->mask_sr);
643 if (!(pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE))
647 int_error_stop(drv_data, "interrupt_transfer: FIFO overrun", -EIO);
652 int_error_stop(drv_data, "interrupt_transfer: FIFO underrun", -EIO);
657 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
658 if (drv_data->read(drv_data)) {
659 int_transfer_complete(drv_data);
666 if (drv_data->read(drv_data)) {
667 int_transfer_complete(drv_data);
670 } while (drv_data->write(drv_data));
672 if (drv_data->read(drv_data)) {
673 int_transfer_complete(drv_data);
677 if (drv_data->tx == drv_data->tx_end) {
681 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
688 if (pxa25x_ssp_comp(drv_data)) {
691 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
693 bytes_left = drv_data->rx_end - drv_data->rx;
694 switch (drv_data->n_bytes) {
703 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
707 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
709 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
716 static void handle_bad_msg(struct driver_data *drv_data)
718 int_stop_and_reset(drv_data);
719 pxa2xx_spi_off(drv_data);
721 dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n");
726 struct driver_data *drv_data = dev_id;
728 u32 mask = drv_data->mask_sr;
737 if (pm_runtime_suspended(drv_data->ssp->dev))
746 status = pxa2xx_spi_read(drv_data, SSSR);
750 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
763 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1);
764 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
766 if (!drv_data->controller->cur_msg) {
767 handle_bad_msg(drv_data);
772 return drv_data->transfer_handler(drv_data);
896 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
898 unsigned long ssp_clk = drv_data->controller->max_speed_hz;
899 const struct ssp_device *ssp = drv_data->ssp;
913 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
917 spi_get_ctldata(drv_data->controller->cur_msg->spi);
920 switch (drv_data->ssp_type) {
925 clk_div = ssp_get_clk_div(drv_data, rate);
946 struct driver_data *drv_data = spi_controller_get_devdata(controller);
951 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
979 if (pxa2xx_spi_flush(drv_data) == 0) {
983 drv_data->tx = (void *)transfer->tx_buf;
984 drv_data->tx_end = drv_data->tx + transfer->len;
985 drv_data->rx = transfer->rx_buf;
986 drv_data->rx_end = drv_data->rx + transfer->len;
992 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
995 drv_data->n_bytes = 1;
996 drv_data->read = drv_data->rx ? u8_reader : null_reader;
997 drv_data->write = drv_data->tx ? u8_writer : null_writer;
999 drv_data->n_bytes = 2;
1000 drv_data->read = drv_data->rx ? u16_reader : null_reader;
1001 drv_data->write = drv_data->tx ? u16_writer : null_writer;
1003 drv_data->n_bytes = 4;
1004 drv_data->read = drv_data->rx ? u32_reader : null_reader;
1005 drv_data->write = drv_data->tx ? u32_writer : null_writer;
1026 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1028 err = pxa2xx_spi_dma_prepare(drv_data, transfer);
1033 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1034 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1036 pxa2xx_spi_dma_start(drv_data);
1039 drv_data->transfer_handler = interrupt_transfer;
1042 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1043 write_SSSR_CS(drv_data, drv_data->clear_sr);
1047 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1048 if (!pxa25x_ssp_comp(drv_data))
1059 if (is_lpss_ssp(drv_data)) {
1060 pxa2xx_spi_update(drv_data, SSIRF, GENMASK(7, 0), chip->lpss_rx_threshold);
1061 pxa2xx_spi_update(drv_data, SSITF, GENMASK(15, 0), chip->lpss_tx_threshold);
1064 if (is_mrfld_ssp(drv_data)) {
1071 pxa2xx_spi_update(drv_data, SFIFOTT, mask, thresh);
1074 if (is_quark_x1000_ssp(drv_data))
1075 pxa2xx_spi_update(drv_data, DDS_RATE, GENMASK(23, 0), chip->dds_rate);
1078 if (!is_mmp2_ssp(drv_data))
1079 pxa_ssp_disable(drv_data->ssp);
1081 if (!pxa25x_ssp_comp(drv_data))
1082 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1085 pxa2xx_spi_update(drv_data, SSCR1, change_mask, cr1);
1088 pxa2xx_spi_update(drv_data, SSCR0, GENMASK(31, 0), cr0);
1091 pxa_ssp_enable(drv_data->ssp);
1093 if (is_mmp2_ssp(drv_data)) {
1094 u8 tx_level = read_SSSR_bits(drv_data, SSSR_TFL_MASK) >> 8;
1101 drv_data->tx += tx_level;
1106 while (drv_data->write(drv_data))
1108 if (drv_data->gpiod_ready) {
1109 gpiod_set_value(drv_data->gpiod_ready, 1);
1111 gpiod_set_value(drv_data->gpiod_ready, 0);
1119 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1126 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1128 int_error_stop(drv_data, "transfer aborted", -EINTR);
1136 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1138 int_stop_and_reset(drv_data);
1141 pxa2xx_spi_off(drv_data);
1150 if (atomic_read(&drv_data->dma_running))
1151 pxa2xx_spi_dma_stop(drv_data);
1156 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1159 pxa2xx_spi_off(drv_data);
1169 struct driver_data *drv_data =
1173 switch (drv_data->ssp_type) {
1195 config = lpss_get_config(drv_data);
1202 if (spi_controller_is_target(drv_data->controller)) {
1219 if (drv_data->ssp_type == CE4100_SSP) {
1227 chip->enable_dma = drv_data->controller_info->enable_dma;
1251 if (spi_controller_is_target(drv_data->controller)) {
1258 if (is_lpss_ssp(drv_data)) {
1264 if (is_mrfld_ssp(drv_data)) {
1288 switch (drv_data->ssp_type) {
1409 struct driver_data *drv_data = spi_controller_get_devdata(controller);
1411 if (has_acpi_companion(drv_data->ssp->dev)) {
1412 switch (drv_data->ssp_type) {
1440 struct driver_data *drv_data;
1465 controller = devm_spi_alloc_target(dev, sizeof(*drv_data));
1467 controller = devm_spi_alloc_host(dev, sizeof(*drv_data));
1474 drv_data = spi_controller_get_devdata(controller);
1475 drv_data->controller = controller;
1476 drv_data->controller_info = platform_info;
1477 drv_data->ssp = ssp;
1497 drv_data->ssp_type = ssp->type;
1499 if (pxa25x_ssp_comp(drv_data)) {
1500 switch (drv_data->ssp_type) {
1509 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1510 drv_data->dma_cr1 = 0;
1511 drv_data->clear_sr = SSSR_ROR;
1512 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1515 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1516 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1517 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1518 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS
1523 drv_data);
1531 status = pxa2xx_spi_dma_setup(drv_data);
1553 if (!pxa25x_ssp_comp(drv_data))
1556 else if (!is_quark_x1000_ssp(drv_data))
1563 switch (drv_data->ssp_type) {
1567 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1571 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1576 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1578 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1593 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1597 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1601 if (!pxa25x_ssp_comp(drv_data))
1602 pxa2xx_spi_write(drv_data, SSTO, 0);
1604 if (!is_quark_x1000_ssp(drv_data))
1605 pxa2xx_spi_write(drv_data, SSPSP, 0);
1607 if (is_lpss_ssp(drv_data)) {
1608 lpss_ssp_setup(drv_data);
1609 config = lpss_get_config(drv_data);
1611 tmp = __lpss_ssp_read_priv(drv_data,
1624 drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
1626 if (IS_ERR(drv_data->gpiod_ready)) {
1627 status = PTR_ERR(drv_data->gpiod_ready);
1638 platform_set_drvdata(pdev, drv_data);
1654 pxa2xx_spi_dma_release(drv_data);
1655 free_irq(ssp->irq, drv_data);
1664 struct driver_data *drv_data = platform_get_drvdata(pdev);
1665 struct ssp_device *ssp = drv_data->ssp;
1669 spi_unregister_controller(drv_data->controller);
1676 if (drv_data->controller_info->enable_dma)
1677 pxa2xx_spi_dma_release(drv_data);
1683 free_irq(ssp->irq, drv_data);
1691 struct driver_data *drv_data = dev_get_drvdata(dev);
1692 struct ssp_device *ssp = drv_data->ssp;
1695 status = spi_controller_suspend(drv_data->controller);
1709 struct driver_data *drv_data = dev_get_drvdata(dev);
1710 struct ssp_device *ssp = drv_data->ssp;
1721 return spi_controller_resume(drv_data->controller);
1726 struct driver_data *drv_data = dev_get_drvdata(dev);
1728 clk_disable_unprepare(drv_data->ssp->clk);
1734 struct driver_data *drv_data = dev_get_drvdata(dev);
1736 return clk_prepare_enable(drv_data->ssp->clk);