Lines Matching refs:virtbase
337 * @virtbase: the virtual memory where the SSP is mapped
371 void __iomem *virtbase;
444 tmp = readw(SSP_CSR(pl022->virtbase));
449 writew(tmp, SSP_CSR(pl022->virtbase));
523 writew((readw(SSP_CR1(pl022->virtbase)) &
524 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
539 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
540 readw(SSP_DR(pl022->virtbase));
541 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
557 writel(chip->cr0, SSP_CR0(pl022->virtbase));
559 writew(chip->cr0, SSP_CR0(pl022->virtbase));
560 writew(chip->cr1, SSP_CR1(pl022->virtbase));
561 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
562 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
563 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
564 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
645 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
646 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
648 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
649 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
651 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
652 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
654 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
655 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
656 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
657 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
682 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
686 readw(SSP_DR(pl022->virtbase));
690 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
694 (u16) readw(SSP_DR(pl022->virtbase));
698 readl(SSP_DR(pl022->virtbase));
711 writew(0x0, SSP_DR(pl022->virtbase));
714 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
717 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
720 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
731 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
735 readw(SSP_DR(pl022->virtbase));
739 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
743 (u16) readw(SSP_DR(pl022->virtbase));
747 readl(SSP_DR(pl022->virtbase));
1260 irq_status = readw(SSP_MIS(pl022->virtbase));
1276 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1286 SSP_IMSC(pl022->virtbase));
1287 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1288 writew((readw(SSP_CR1(pl022->virtbase)) &
1289 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1301 writew((readw(SSP_IMSC(pl022->virtbase)) &
1303 SSP_IMSC(pl022->virtbase));
1313 SSP_IMSC(pl022->virtbase));
1314 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1434 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
1469 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1470 SSP_CR1(pl022->virtbase));
1471 writew(irqflags, SSP_IMSC(pl022->virtbase));
1480 read_cr0 = readl(SSP_CR0(pl022->virtbase));
1482 read_cr0 = readw(SSP_CR0(pl022->virtbase));
1483 read_cr1 = readw(SSP_CR1(pl022->virtbase));
1484 read_dmacr = readw(SSP_DMACR(pl022->virtbase));
1485 read_sr = readw(SSP_SR(pl022->virtbase));
1536 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1537 SSP_CR1(pl022->virtbase));
1610 writew((readw(SSP_CR1(pl022->virtbase)) &
1611 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
2162 pl022->virtbase = devm_ioremap(dev, adev->res.start,
2164 if (pl022->virtbase == NULL) {
2169 &adev->res.start, pl022->virtbase);
2189 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2190 SSP_CR1(pl022->virtbase));