Lines Matching refs:pl022
27 #include <linux/amba/pl022.h>
333 * struct pl022 - This is the private SSP driver data structure
367 struct pl022 {
433 * @pl022: SSP driver private data structure
440 static void internal_cs_control(struct pl022 *pl022, u32 command)
444 tmp = readw(SSP_CSR(pl022->virtbase));
446 tmp &= ~BIT(pl022->cur_cs);
448 tmp |= BIT(pl022->cur_cs);
449 writew(tmp, SSP_CSR(pl022->virtbase));
452 static void pl022_cs_control(struct pl022 *pl022, u32 command)
454 if (pl022->vendor->internal_cs_ctrl)
455 internal_cs_control(pl022, command);
456 else if (pl022->cur_gpiod)
465 gpiod_set_value(pl022->cur_gpiod, !command);
472 * @pl022: SSP driver private data structure
474 static void giveback(struct pl022 *pl022)
477 pl022->next_msg_cs_active = false;
479 last_transfer = list_last_entry(&pl022->cur_msg->transfers,
503 next_msg = spi_get_next_queued_message(pl022->host);
509 if (next_msg && next_msg->spi != pl022->cur_msg->spi)
511 if (!next_msg || pl022->cur_msg->state == STATE_ERROR)
512 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
514 pl022->next_msg_cs_active = true;
518 pl022->cur_msg = NULL;
519 pl022->cur_transfer = NULL;
520 pl022->cur_chip = NULL;
523 writew((readw(SSP_CR1(pl022->virtbase)) &
524 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
526 spi_finalize_current_message(pl022->host);
531 * @pl022: SSP driver private data structure
533 static int flush(struct pl022 *pl022)
537 dev_dbg(&pl022->adev->dev, "flush\n");
539 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
540 readw(SSP_DR(pl022->virtbase));
541 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
543 pl022->exp_fifo_level = 0;
550 * @pl022: SSP driver private data structure
552 static void restore_state(struct pl022 *pl022)
554 struct chip_data *chip = pl022->cur_chip;
556 if (pl022->vendor->extended_cr)
557 writel(chip->cr0, SSP_CR0(pl022->virtbase));
559 writew(chip->cr0, SSP_CR0(pl022->virtbase));
560 writew(chip->cr1, SSP_CR1(pl022->virtbase));
561 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
562 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
563 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
564 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
640 * @pl022: SSP driver private data structure
642 static void load_ssp_default_config(struct pl022 *pl022)
644 if (pl022->vendor->pl023) {
645 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
646 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
647 } else if (pl022->vendor->extended_cr) {
648 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
649 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
651 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
652 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
654 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
655 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
656 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
657 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
662 * set in pl022.
664 static void readwriter(struct pl022 *pl022)
677 dev_dbg(&pl022->adev->dev,
679 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
682 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
683 && (pl022->rx < pl022->rx_end)) {
684 switch (pl022->read) {
686 readw(SSP_DR(pl022->virtbase));
689 *(u8 *) (pl022->rx) =
690 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
693 *(u16 *) (pl022->rx) =
694 (u16) readw(SSP_DR(pl022->virtbase));
697 *(u32 *) (pl022->rx) =
698 readl(SSP_DR(pl022->virtbase));
701 pl022->rx += (pl022->cur_chip->n_bytes);
702 pl022->exp_fifo_level--;
707 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
708 && (pl022->tx < pl022->tx_end)) {
709 switch (pl022->write) {
711 writew(0x0, SSP_DR(pl022->virtbase));
714 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
717 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
720 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
723 pl022->tx += (pl022->cur_chip->n_bytes);
724 pl022->exp_fifo_level++;
731 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
732 && (pl022->rx < pl022->rx_end)) {
733 switch (pl022->read) {
735 readw(SSP_DR(pl022->virtbase));
738 *(u8 *) (pl022->rx) =
739 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
742 *(u16 *) (pl022->rx) =
743 (u16) readw(SSP_DR(pl022->virtbase));
746 *(u32 *) (pl022->rx) =
747 readl(SSP_DR(pl022->virtbase));
750 pl022->rx += (pl022->cur_chip->n_bytes);
751 pl022->exp_fifo_level--;
762 * @pl022: SSP driver private data structure
769 static void *next_transfer(struct pl022 *pl022)
771 struct spi_message *msg = pl022->cur_msg;
772 struct spi_transfer *trans = pl022->cur_transfer;
776 pl022->cur_transfer =
789 static void unmap_free_dma_scatter(struct pl022 *pl022)
792 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
793 pl022->sgt_tx.nents, DMA_TO_DEVICE);
794 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
795 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
796 sg_free_table(&pl022->sgt_rx);
797 sg_free_table(&pl022->sgt_tx);
802 struct pl022 *pl022 = data;
803 struct spi_message *msg = pl022->cur_msg;
805 BUG_ON(!pl022->sgt_rx.sgl);
818 dma_sync_sg_for_cpu(&pl022->adev->dev,
819 pl022->sgt_rx.sgl,
820 pl022->sgt_rx.nents,
823 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
824 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
833 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
834 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
846 unmap_free_dma_scatter(pl022);
849 msg->actual_length += pl022->cur_transfer->len;
851 msg->state = next_transfer(pl022);
852 if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change)
853 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
854 tasklet_schedule(&pl022->pump_transfers);
857 static void setup_dma_scatter(struct pl022 *pl022,
884 dev_dbg(&pl022->adev->dev,
895 sg_set_page(sg, virt_to_page(pl022->dummypage),
898 dev_dbg(&pl022->adev->dev,
909 * @pl022: SSP driver's private data structure
911 static int configure_dma(struct pl022 *pl022)
914 .src_addr = SSP_DR(pl022->phybase),
919 .dst_addr = SSP_DR(pl022->phybase),
926 struct dma_chan *rxchan = pl022->dma_rx_channel;
927 struct dma_chan *txchan = pl022->dma_tx_channel;
941 switch (pl022->rx_lev_trig) {
958 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
962 switch (pl022->tx_lev_trig) {
979 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
983 switch (pl022->read) {
999 switch (pl022->write) {
1026 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
1027 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
1029 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
1033 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
1038 setup_dma_scatter(pl022, pl022->rx,
1039 pl022->cur_transfer->len, &pl022->sgt_rx);
1040 setup_dma_scatter(pl022, pl022->tx,
1041 pl022->cur_transfer->len, &pl022->sgt_tx);
1044 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1045 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1049 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1050 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1056 pl022->sgt_rx.sgl,
1064 pl022->sgt_tx.sgl,
1073 rxdesc->callback_param = pl022;
1080 pl022->dma_running = true;
1088 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
1089 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1091 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
1092 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
1094 sg_free_table(&pl022->sgt_tx);
1096 sg_free_table(&pl022->sgt_rx);
1101 static int pl022_dma_probe(struct pl022 *pl022)
1112 pl022->dma_rx_channel = dma_request_channel(mask,
1113 pl022->host_info->dma_filter,
1114 pl022->host_info->dma_rx_param);
1115 if (!pl022->dma_rx_channel) {
1116 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
1120 pl022->dma_tx_channel = dma_request_channel(mask,
1121 pl022->host_info->dma_filter,
1122 pl022->host_info->dma_tx_param);
1123 if (!pl022->dma_tx_channel) {
1124 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
1128 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1129 if (!pl022->dummypage)
1132 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1133 dma_chan_name(pl022->dma_rx_channel),
1134 dma_chan_name(pl022->dma_tx_channel));
1139 dma_release_channel(pl022->dma_tx_channel);
1141 dma_release_channel(pl022->dma_rx_channel);
1142 pl022->dma_rx_channel = NULL;
1144 dev_err(&pl022->adev->dev,
1149 static int pl022_dma_autoprobe(struct pl022 *pl022)
1151 struct device *dev = &pl022->adev->dev;
1162 pl022->dma_rx_channel = chan;
1170 pl022->dma_tx_channel = chan;
1172 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1173 if (!pl022->dummypage) {
1181 dma_release_channel(pl022->dma_tx_channel);
1182 pl022->dma_tx_channel = NULL;
1184 dma_release_channel(pl022->dma_rx_channel);
1185 pl022->dma_rx_channel = NULL;
1190 static void terminate_dma(struct pl022 *pl022)
1192 struct dma_chan *rxchan = pl022->dma_rx_channel;
1193 struct dma_chan *txchan = pl022->dma_tx_channel;
1197 unmap_free_dma_scatter(pl022);
1198 pl022->dma_running = false;
1201 static void pl022_dma_remove(struct pl022 *pl022)
1203 if (pl022->dma_running)
1204 terminate_dma(pl022);
1205 if (pl022->dma_tx_channel)
1206 dma_release_channel(pl022->dma_tx_channel);
1207 if (pl022->dma_rx_channel)
1208 dma_release_channel(pl022->dma_rx_channel);
1209 kfree(pl022->dummypage);
1213 static inline int configure_dma(struct pl022 *pl022)
1218 static inline int pl022_dma_autoprobe(struct pl022 *pl022)
1223 static inline int pl022_dma_probe(struct pl022 *pl022)
1228 static inline void pl022_dma_remove(struct pl022 *pl022)
1248 struct pl022 *pl022 = dev_id;
1249 struct spi_message *msg = pl022->cur_msg;
1253 dev_err(&pl022->adev->dev,
1260 irq_status = readw(SSP_MIS(pl022->virtbase));
1275 dev_err(&pl022->adev->dev, "FIFO overrun\n");
1276 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1277 dev_err(&pl022->adev->dev,
1286 SSP_IMSC(pl022->virtbase));
1287 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1288 writew((readw(SSP_CR1(pl022->virtbase)) &
1289 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1293 tasklet_schedule(&pl022->pump_transfers);
1297 readwriter(pl022);
1299 if (pl022->tx == pl022->tx_end) {
1301 writew((readw(SSP_IMSC(pl022->virtbase)) &
1303 SSP_IMSC(pl022->virtbase));
1311 if (pl022->rx >= pl022->rx_end) {
1313 SSP_IMSC(pl022->virtbase));
1314 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1315 if (unlikely(pl022->rx > pl022->rx_end)) {
1316 dev_warn(&pl022->adev->dev, "read %u surplus "
1319 (u32) (pl022->rx - pl022->rx_end));
1322 msg->actual_length += pl022->cur_transfer->len;
1324 msg->state = next_transfer(pl022);
1325 if (msg->state != STATE_DONE && pl022->cur_transfer->cs_change)
1326 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1327 tasklet_schedule(&pl022->pump_transfers);
1338 static int set_up_next_transfer(struct pl022 *pl022,
1344 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1346 dev_err(&pl022->adev->dev,
1349 pl022->cur_transfer->len,
1350 pl022->cur_chip->n_bytes);
1351 dev_err(&pl022->adev->dev, "skipping this message\n");
1354 pl022->tx = (void *)transfer->tx_buf;
1355 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1356 pl022->rx = (void *)transfer->rx_buf;
1357 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1358 pl022->write =
1359 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1360 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1372 struct pl022 *pl022 = (struct pl022 *) data;
1378 message = pl022->cur_msg;
1379 transfer = pl022->cur_transfer;
1384 giveback(pl022);
1391 giveback(pl022);
1408 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1414 if (set_up_next_transfer(pl022, transfer)) {
1417 giveback(pl022);
1421 flush(pl022);
1423 if (pl022->cur_chip->enable_dma) {
1424 if (configure_dma(pl022)) {
1425 dev_dbg(&pl022->adev->dev,
1434 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
1437 static void do_interrupt_dma_transfer(struct pl022 *pl022)
1446 if (!pl022->next_msg_cs_active)
1447 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1449 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1451 pl022->cur_msg->state = STATE_ERROR;
1452 pl022->cur_msg->status = -EIO;
1453 giveback(pl022);
1457 if (pl022->cur_chip->enable_dma) {
1459 if (configure_dma(pl022)) {
1460 dev_dbg(&pl022->adev->dev,
1469 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1470 SSP_CR1(pl022->virtbase));
1471 writew(irqflags, SSP_IMSC(pl022->virtbase));
1474 static void print_current_status(struct pl022 *pl022)
1479 if (pl022->vendor->extended_cr)
1480 read_cr0 = readl(SSP_CR0(pl022->virtbase));
1482 read_cr0 = readw(SSP_CR0(pl022->virtbase));
1483 read_cr1 = readw(SSP_CR1(pl022->virtbase));
1484 read_dmacr = readw(SSP_DMACR(pl022->virtbase));
1485 read_sr = readw(SSP_SR(pl022->virtbase));
1487 dev_warn(&pl022->adev->dev, "spi-pl022 CR0: %x\n", read_cr0);
1488 dev_warn(&pl022->adev->dev, "spi-pl022 CR1: %x\n", read_cr1);
1489 dev_warn(&pl022->adev->dev, "spi-pl022 DMACR: %x\n", read_dmacr);
1490 dev_warn(&pl022->adev->dev, "spi-pl022 SR: %x\n", read_sr);
1491 dev_warn(&pl022->adev->dev,
1492 "spi-pl022 exp_fifo_level/fifodepth: %u/%d\n",
1493 pl022->exp_fifo_level,
1494 pl022->vendor->fifodepth);
1498 static void do_polling_transfer(struct pl022 *pl022)
1505 message = pl022->cur_msg;
1511 transfer = pl022->cur_transfer;
1520 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1524 if (!pl022->next_msg_cs_active)
1525 pl022_cs_control(pl022, SSP_CHIP_SELECT);
1529 if (set_up_next_transfer(pl022, transfer)) {
1535 flush(pl022);
1536 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1537 SSP_CR1(pl022->virtbase));
1539 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
1542 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1544 readwriter(pl022);
1546 dev_warn(&pl022->adev->dev,
1549 print_current_status(pl022);
1556 message->actual_length += pl022->cur_transfer->len;
1558 message->state = next_transfer(pl022);
1560 && pl022->cur_transfer->cs_change)
1561 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
1572 giveback(pl022);
1579 struct pl022 *pl022 = spi_controller_get_devdata(host);
1582 pl022->cur_msg = msg;
1585 pl022->cur_transfer = list_entry(msg->transfers.next,
1589 pl022->cur_chip = spi_get_ctldata(msg->spi);
1590 pl022->cur_cs = spi_get_chipselect(msg->spi, 0);
1592 pl022->cur_gpiod = spi_get_csgpiod(msg->spi, 0);
1594 restore_state(pl022);
1595 flush(pl022);
1597 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1598 do_polling_transfer(pl022);
1600 do_interrupt_dma_transfer(pl022);
1607 struct pl022 *pl022 = spi_controller_get_devdata(host);
1610 writew((readw(SSP_CR1(pl022->virtbase)) &
1611 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1616 static int verify_controller_parameters(struct pl022 *pl022,
1621 dev_err(&pl022->adev->dev,
1626 (!pl022->vendor->unidir)) {
1627 dev_err(&pl022->adev->dev,
1634 dev_err(&pl022->adev->dev,
1641 dev_err(&pl022->adev->dev,
1652 if (pl022->vendor->fifodepth < 16) {
1653 dev_err(&pl022->adev->dev,
1659 if (pl022->vendor->fifodepth < 32) {
1660 dev_err(&pl022->adev->dev,
1666 dev_err(&pl022->adev->dev,
1677 if (pl022->vendor->fifodepth < 16) {
1678 dev_err(&pl022->adev->dev,
1684 if (pl022->vendor->fifodepth < 32) {
1685 dev_err(&pl022->adev->dev,
1691 dev_err(&pl022->adev->dev,
1698 dev_err(&pl022->adev->dev,
1704 dev_err(&pl022->adev->dev,
1709 if (pl022->vendor->extended_cr) {
1714 dev_err(&pl022->adev->dev,
1720 dev_err(&pl022->adev->dev,
1736 static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1744 rate = clk_get_rate(pl022->clk);
1751 dev_warn(&pl022->adev->dev,
1756 dev_err(&pl022->adev->dev,
1798 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
1803 dev_dbg(&pl022->adev->dev,
1806 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1847 struct pl022 *pl022 = spi_controller_get_devdata(spi->controller);
1874 of_property_read_u32(np, "pl022,interface",
1876 of_property_read_u32(np, "pl022,com-mode",
1878 of_property_read_u32(np, "pl022,rx-level-trig",
1880 of_property_read_u32(np, "pl022,tx-level-trig",
1882 of_property_read_u32(np, "pl022,ctrl-len",
1884 of_property_read_u32(np, "pl022,wait-state",
1886 of_property_read_u32(np, "pl022,duplex",
1906 status = calculate_effective_freq(pl022,
1925 status = verify_controller_parameters(pl022, chip_info);
1931 pl022->rx_lev_trig = chip_info->rx_lev_trig;
1932 pl022->tx_lev_trig = chip_info->tx_lev_trig;
1938 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
1942 pl022->vendor->max_bpw);
1967 && ((pl022->host_info)->enable_dma)) {
1986 if (pl022->vendor->extended_cr) {
1989 if (pl022->vendor->pl023) {
2042 if (pl022->vendor->loopback) {
2094 of_property_read_u32(np, "pl022,autosuspend-delay",
2096 pd->rt = of_property_read_bool(np, "pl022,rt");
2107 struct pl022 *pl022 = NULL; /*Data for this driver */
2121 host = spi_alloc_host(dev, sizeof(struct pl022));
2127 pl022 = spi_controller_get_devdata(host);
2128 pl022->host = host;
2129 pl022->host_info = platform_info;
2130 pl022->adev = adev;
2131 pl022->vendor = id->data;
2149 * always MS bit first on the original pl022.
2152 if (pl022->vendor->extended_cr)
2161 pl022->phybase = adev->res.start;
2162 pl022->virtbase = devm_ioremap(dev, adev->res.start,
2164 if (pl022->virtbase == NULL) {
2169 &adev->res.start, pl022->virtbase);
2171 pl022->clk = devm_clk_get(&adev->dev, NULL);
2172 if (IS_ERR(pl022->clk)) {
2173 status = PTR_ERR(pl022->clk);
2178 status = clk_prepare_enable(pl022->clk);
2185 tasklet_init(&pl022->pump_transfers, pump_transfers,
2186 (unsigned long)pl022);
2189 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2190 SSP_CR1(pl022->virtbase));
2191 load_ssp_default_config(pl022);
2194 0, "pl022", pl022);
2201 status = pl022_dma_autoprobe(pl022);
2211 status = pl022_dma_probe(pl022);
2217 amba_set_drvdata(adev, pl022);
2241 pl022_dma_remove(pl022);
2243 clk_disable_unprepare(pl022->clk);
2256 struct pl022 *pl022 = amba_get_drvdata(adev);
2258 if (!pl022)
2267 load_ssp_default_config(pl022);
2268 if (pl022->host_info->enable_dma)
2269 pl022_dma_remove(pl022);
2271 clk_disable_unprepare(pl022->clk);
2273 tasklet_disable(&pl022->pump_transfers);
2279 struct pl022 *pl022 = dev_get_drvdata(dev);
2282 ret = spi_controller_suspend(pl022->host);
2288 spi_controller_resume(pl022->host);
2300 struct pl022 *pl022 = dev_get_drvdata(dev);
2308 ret = spi_controller_resume(pl022->host);
2319 struct pl022 *pl022 = dev_get_drvdata(dev);
2321 clk_disable_unprepare(pl022->clk);
2329 struct pl022 *pl022 = dev_get_drvdata(dev);
2332 clk_prepare_enable(pl022->clk);
2430 .name = "ssp-pl022",