Lines Matching refs:SSP_WRITE_BITS
42 #define SSP_WRITE_BITS(reg, val, mask, sb) \
1970 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1972 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1977 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1979 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1991 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1995 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1997 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1999 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2001 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
2004 SSP_WRITE_BITS(chip->cr0, bits - 1,
2014 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
2015 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
2016 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
2018 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
2021 SSP_WRITE_BITS(chip->cr0, bits - 1,
2023 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2032 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
2038 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
2040 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
2047 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2049 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2050 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2051 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,