Lines Matching defs:chip_info
1617 struct pl022_config_chip const *chip_info)
1619 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1620 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1625 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1632 if ((chip_info->hierarchy != SSP_MASTER)
1633 && (chip_info->hierarchy != SSP_SLAVE)) {
1638 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1639 && (chip_info->com_mode != DMA_TRANSFER)
1640 && (chip_info->com_mode != POLLING_TRANSFER)) {
1645 switch (chip_info->rx_lev_trig) {
1670 switch (chip_info->tx_lev_trig) {
1695 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1696 if ((chip_info->ctrl_len < SSP_BITS_4)
1697 || (chip_info->ctrl_len > SSP_BITS_32)) {
1702 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1703 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1710 if ((chip_info->duplex !=
1712 && (chip_info->duplex !=
1719 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX) {
1842 struct pl022_config_chip const *chip_info;
1867 chip_info = spi->controller_data;
1869 if (chip_info == NULL) {
1889 chip_info = &chip_info_dt;
1891 chip_info = &pl022_default_chip_info;
1904 if ((0 == chip_info->clk_freq.cpsdvsr)
1905 && (0 == chip_info->clk_freq.scr)) {
1912 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1925 status = verify_controller_parameters(pl022, chip_info);
1931 pl022->rx_lev_trig = chip_info->rx_lev_trig;
1932 pl022->tx_lev_trig = chip_info->tx_lev_trig;
1935 chip->xfer_type = chip_info->com_mode;
1966 if ((chip_info->com_mode == DMA_TRANSFER)
1991 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1995 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1997 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1999 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2001 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
2016 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
2018 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
2023 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
2050 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
2051 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,