Lines Matching refs:sqi
165 static int pic32_sqi_set_clk_rate(struct pic32_sqi *sqi, u32 sck)
170 div = clk_get_rate(sqi->base_clk) / (2 * sck);
173 val = readl(sqi->regs + PESQI_CLK_CTRL_REG);
177 writel(val, sqi->regs + PESQI_CLK_CTRL_REG);
180 return readl_poll_timeout(sqi->regs + PESQI_CLK_CTRL_REG, val,
184 static inline void pic32_sqi_enable_int(struct pic32_sqi *sqi)
188 writel(mask, sqi->regs + PESQI_INT_ENABLE_REG);
190 writel(mask, sqi->regs + PESQI_INT_SIGEN_REG);
193 static inline void pic32_sqi_disable_int(struct pic32_sqi *sqi)
195 writel(0, sqi->regs + PESQI_INT_ENABLE_REG);
196 writel(0, sqi->regs + PESQI_INT_SIGEN_REG);
201 struct pic32_sqi *sqi = dev_id;
204 enable = readl(sqi->regs + PESQI_INT_ENABLE_REG);
205 status = readl(sqi->regs + PESQI_INT_STAT_REG);
230 complete(&sqi->xfer_done);
235 writel(enable, sqi->regs + PESQI_INT_ENABLE_REG);
240 static struct ring_desc *ring_desc_get(struct pic32_sqi *sqi)
244 if (list_empty(&sqi->bd_list_free))
247 rdesc = list_first_entry(&sqi->bd_list_free, struct ring_desc, list);
248 list_move_tail(&rdesc->list, &sqi->bd_list_used);
252 static void ring_desc_put(struct pic32_sqi *sqi, struct ring_desc *rdesc)
254 list_move(&rdesc->list, &sqi->bd_list_free);
257 static int pic32_sqi_one_transfer(struct pic32_sqi *sqi,
298 rdesc = ring_desc_get(sqi);
321 struct pic32_sqi *sqi = spi_controller_get_devdata(host);
324 pic32_setbits(sqi->regs + PESQI_CONF_REG, PESQI_EN);
326 pic32_setbits(sqi->regs + PESQI_CLK_CTRL_REG, PESQI_CLK_EN);
345 struct pic32_sqi *sqi;
350 sqi = spi_controller_get_devdata(host);
352 reinit_completion(&sqi->xfer_done);
359 if (sqi->cur_spi != spi) {
361 if (sqi->cur_speed != spi->max_speed_hz) {
362 sqi->cur_speed = spi->max_speed_hz;
363 ret = pic32_sqi_set_clk_rate(sqi, spi->max_speed_hz);
370 if (sqi->cur_mode != mode) {
371 val = readl(sqi->regs + PESQI_CONF_REG);
378 writel(val, sqi->regs + PESQI_CONF_REG);
380 sqi->cur_mode = mode;
382 sqi->cur_spi = spi;
387 ret = pic32_sqi_one_transfer(sqi, msg, xfer);
397 rdesc = list_last_entry(&sqi->bd_list_used, struct ring_desc, list);
402 rdesc = list_first_entry(&sqi->bd_list_used, struct ring_desc, list);
403 writel(rdesc->bd_dma, sqi->regs + PESQI_BD_BASE_ADDR_REG);
406 pic32_sqi_enable_int(sqi);
410 writel(val, sqi->regs + PESQI_BD_CTRL_REG);
413 timeout = wait_for_completion_timeout(&sqi->xfer_done, 5 * HZ);
415 dev_err(&sqi->host->dev, "wait timedout/interrupted\n");
425 writel(0, sqi->regs + PESQI_BD_CTRL_REG);
427 pic32_sqi_disable_int(sqi);
431 &sqi->bd_list_used, list) {
435 ring_desc_put(sqi, rdesc);
444 struct pic32_sqi *sqi = spi_controller_get_devdata(host);
447 pic32_clrbits(sqi->regs + PESQI_CLK_CTRL_REG, PESQI_CLK_EN);
449 pic32_clrbits(sqi->regs + PESQI_CONF_REG, PESQI_EN);
454 static int ring_desc_ring_alloc(struct pic32_sqi *sqi)
461 sqi->bd = dma_alloc_coherent(&sqi->host->dev,
463 &sqi->bd_dma, GFP_KERNEL);
464 if (!sqi->bd) {
465 dev_err(&sqi->host->dev, "failed allocating dma buffer\n");
470 sqi->ring = kcalloc(PESQI_BD_COUNT, sizeof(*rdesc), GFP_KERNEL);
471 if (!sqi->ring) {
472 dma_free_coherent(&sqi->host->dev,
474 sqi->bd, sqi->bd_dma);
478 bd = (struct buf_desc *)sqi->bd;
480 INIT_LIST_HEAD(&sqi->bd_list_free);
481 INIT_LIST_HEAD(&sqi->bd_list_used);
484 for (i = 0, rdesc = sqi->ring; i < PESQI_BD_COUNT; i++, rdesc++) {
487 rdesc->bd_dma = sqi->bd_dma + (void *)&bd[i] - (void *)bd;
488 list_add_tail(&rdesc->list, &sqi->bd_list_free);
492 for (i = 0, rdesc = sqi->ring; i < PESQI_BD_COUNT - 1; i++)
499 static void ring_desc_ring_free(struct pic32_sqi *sqi)
501 dma_free_coherent(&sqi->host->dev,
503 sqi->bd, sqi->bd_dma);
504 kfree(sqi->ring);
507 static void pic32_sqi_hw_init(struct pic32_sqi *sqi)
519 writel(PESQI_SOFT_RESET, sqi->regs + PESQI_CONF_REG);
522 readl_poll_timeout_atomic(sqi->regs + PESQI_CONF_REG, val,
526 pic32_sqi_disable_int(sqi);
532 val = readl(sqi->regs + PESQI_CMD_THRES_REG);
536 writel(val, sqi->regs + PESQI_CMD_THRES_REG);
538 val = readl(sqi->regs + PESQI_INT_THRES_REG);
542 writel(val, sqi->regs + PESQI_INT_THRES_REG);
545 val = readl(sqi->regs + PESQI_CONF_REG);
550 writel(val, sqi->regs + PESQI_CONF_REG);
560 writel(val, sqi->regs + PESQI_CONF_REG);
563 writel(0, sqi->regs + PESQI_BD_POLL_CTRL_REG);
565 sqi->cur_speed = 0;
566 sqi->cur_mode = -1;
572 struct pic32_sqi *sqi;
575 host = spi_alloc_host(&pdev->dev, sizeof(*sqi));
579 sqi = spi_controller_get_devdata(host);
580 sqi->host = host;
582 sqi->regs = devm_platform_ioremap_resource(pdev, 0);
583 if (IS_ERR(sqi->regs)) {
584 ret = PTR_ERR(sqi->regs);
589 sqi->irq = platform_get_irq(pdev, 0);
590 if (sqi->irq < 0) {
591 ret = sqi->irq;
596 sqi->sys_clk = devm_clk_get(&pdev->dev, "reg_ck");
597 if (IS_ERR(sqi->sys_clk)) {
598 ret = PTR_ERR(sqi->sys_clk);
603 sqi->base_clk = devm_clk_get(&pdev->dev, "spi_ck");
604 if (IS_ERR(sqi->base_clk)) {
605 ret = PTR_ERR(sqi->base_clk);
610 ret = clk_prepare_enable(sqi->sys_clk);
616 ret = clk_prepare_enable(sqi->base_clk);
619 clk_disable_unprepare(sqi->sys_clk);
623 init_completion(&sqi->xfer_done);
626 pic32_sqi_hw_init(sqi);
629 ret = ring_desc_ring_alloc(sqi);
636 ret = request_irq(sqi->irq, pic32_sqi_isr, 0,
637 dev_name(&pdev->dev), sqi);
639 dev_err(&pdev->dev, "request_irq(%d), failed\n", sqi->irq);
645 host->max_speed_hz = clk_get_rate(sqi->base_clk);
661 free_irq(sqi->irq, sqi);
665 platform_set_drvdata(pdev, sqi);
670 ring_desc_ring_free(sqi);
673 clk_disable_unprepare(sqi->base_clk);
674 clk_disable_unprepare(sqi->sys_clk);
683 struct pic32_sqi *sqi = platform_get_drvdata(pdev);
686 free_irq(sqi->irq, sqi);
687 ring_desc_ring_free(sqi);
690 clk_disable_unprepare(sqi->base_clk);
691 clk_disable_unprepare(sqi->sys_clk);
695 {.compatible = "microchip,pic32mzda-sqi",},
702 .name = "sqi-pic32",