Lines Matching defs:spi
28 #include <linux/spi/spi.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
161 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
164 struct omap2_mcspi_cs *cs = spi->controller_state;
169 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
171 struct omap2_mcspi_cs *cs = spi->controller_state;
176 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
178 struct omap2_mcspi_cs *cs = spi->controller_state;
183 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
185 struct omap2_mcspi_cs *cs = spi->controller_state;
188 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
189 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
202 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
207 l = mcspi_cached_chconf0(spi);
219 mcspi_write_chconf0(spi, l);
222 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
224 struct omap2_mcspi_cs *cs = spi->controller_state;
233 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
235 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
238 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
240 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
247 if (spi->mode & SPI_CS_HIGH)
250 if (spi->controller_state) {
257 l = mcspi_cached_chconf0(spi);
264 mcspi_write_chconf0(spi, l);
293 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
296 struct spi_controller *ctlr = spi->controller;
297 struct omap2_mcspi_cs *cs = spi->controller_state;
305 chconf = mcspi_cached_chconf0(spi);
332 mcspi_write_chconf0(spi, chconf);
345 mcspi_write_chconf0(spi, chconf);
382 struct spi_device *spi = data;
383 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
384 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
387 omap2_mcspi_set_dma_req(spi, 1, 0);
394 struct spi_device *spi = data;
395 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
396 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
399 omap2_mcspi_set_dma_req(spi, 0, 0);
404 static void omap2_mcspi_tx_dma(struct spi_device *spi,
412 mcspi = spi_controller_get_devdata(spi->controller);
413 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
423 tx->callback_param = spi;
429 omap2_mcspi_set_dma_req(spi, 0, 1);
433 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
446 struct omap2_mcspi_cs *cs = spi->controller_state;
450 mcspi = spi_controller_get_devdata(spi->controller);
451 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
463 l = mcspi_cached_chconf0(spi);
500 dev_err(&spi->dev, "sg_split failed\n");
509 tx->callback_param = spi;
516 omap2_mcspi_set_dma_req(spi, 1, 1);
521 omap2_mcspi_set_dma_req(spi, 1, 0);
535 omap2_mcspi_set_enable(spi, 0);
546 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
555 dev_err(&spi->dev, "DMA RX penultimate word empty\n");
557 omap2_mcspi_set_enable(spi, 1);
564 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
572 dev_err(&spi->dev, "DMA RX last word empty\n");
575 omap2_mcspi_set_enable(spi, 1);
580 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
583 struct omap2_mcspi_cs *cs = spi->controller_state;
595 mcspi = spi_controller_get_devdata(spi->controller);
596 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
628 if (spi_controller_is_target(spi->controller))
629 mcspi_write_reg(spi->controller,
632 omap2_mcspi_tx_dma(spi, xfer, cfg);
636 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
644 omap2_mcspi_set_dma_req(spi, 0, 0);
659 dev_err(&spi->dev, "EOW timed out\n");
672 dev_err(&spi->dev, "TXFFE timed out\n");
677 dev_err(&spi->dev, "TXS timed out\n");
682 dev_err(&spi->dev, "EOT timed out\n");
689 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
691 struct omap2_mcspi_cs *cs = spi->controller_state;
704 l = mcspi_cached_chconf0(spi);
727 dev_err(&spi->dev, "TXS timed out\n");
730 dev_vdbg(&spi->dev, "write-%d %02x\n",
737 dev_err(&spi->dev, "RXS timed out\n");
743 omap2_mcspi_set_enable(spi, 0);
745 dev_vdbg(&spi->dev, "read-%d %02x\n",
749 dev_err(&spi->dev,
755 omap2_mcspi_set_enable(spi, 0);
759 dev_vdbg(&spi->dev, "read-%d %02x\n",
776 dev_err(&spi->dev, "TXS timed out\n");
779 dev_vdbg(&spi->dev, "write-%d %04x\n",
786 dev_err(&spi->dev, "RXS timed out\n");
792 omap2_mcspi_set_enable(spi, 0);
794 dev_vdbg(&spi->dev, "read-%d %04x\n",
798 dev_err(&spi->dev,
804 omap2_mcspi_set_enable(spi, 0);
808 dev_vdbg(&spi->dev, "read-%d %04x\n",
825 dev_err(&spi->dev, "TXS timed out\n");
828 dev_vdbg(&spi->dev, "write-%d %08x\n",
835 dev_err(&spi->dev, "RXS timed out\n");
841 omap2_mcspi_set_enable(spi, 0);
843 dev_vdbg(&spi->dev, "read-%d %08x\n",
847 dev_err(&spi->dev,
853 omap2_mcspi_set_enable(spi, 0);
857 dev_vdbg(&spi->dev, "read-%d %08x\n",
869 dev_err(&spi->dev, "TXS timed out\n");
872 dev_err(&spi->dev, "EOT timed out\n");
878 omap2_mcspi_set_enable(spi, 0);
881 omap2_mcspi_set_enable(spi, 1);
897 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
900 struct omap2_mcspi_cs *cs = spi->controller_state;
903 u8 word_len = spi->bits_per_word;
904 u32 speed_hz = spi->max_speed_hz;
906 mcspi = spi_controller_get_devdata(spi->controller);
930 l = mcspi_cached_chconf0(spi);
950 if (!(spi->mode & SPI_CS_HIGH))
965 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
969 if (spi->mode & SPI_CPOL)
973 if (spi->mode & SPI_CPHA)
978 mcspi_write_chconf0(spi, l);
980 cs->mode = spi->mode;
982 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
984 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
985 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
1043 static void omap2_mcspi_cleanup(struct spi_device *spi)
1047 if (spi->controller_state) {
1049 cs = spi->controller_state;
1056 static int omap2_mcspi_setup(struct spi_device *spi)
1060 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
1062 struct omap2_mcspi_cs *cs = spi->controller_state;
1068 cs->base = mcspi->base + spi_get_chipselect(spi, 0) * 0x14;
1069 cs->phys = mcspi->phys + spi_get_chipselect(spi, 0) * 0x14;
1073 spi->controller_state = cs;
1082 omap2_mcspi_cleanup(spi);
1087 ret = omap2_mcspi_setup_transfer(spi, NULL);
1089 omap2_mcspi_cleanup(spi);
1128 struct spi_device *spi,
1148 mcspi_dma = mcspi->dma_channels + spi_get_chipselect(spi, 0);
1149 cs = spi->controller_state;
1150 cd = spi->controller_data;
1153 * The target driver could have changed spi->mode in which case
1159 if (spi->mode != cs->mode)
1162 omap2_mcspi_set_enable(spi, 0);
1164 if (spi_get_csgpiod(spi, 0))
1165 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1168 (t->speed_hz != spi->max_speed_hz) ||
1169 (t->bits_per_word != spi->bits_per_word)) {
1171 status = omap2_mcspi_setup_transfer(spi, t);
1174 if (t->speed_hz == spi->max_speed_hz &&
1175 t->bits_per_word == spi->bits_per_word)
1183 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1186 chconf = mcspi_cached_chconf0(spi);
1201 mcspi_write_chconf0(spi, chconf);
1208 ctlr->can_dma(ctlr, spi, t))
1209 omap2_mcspi_set_fifo(spi, t, 1);
1211 omap2_mcspi_set_enable(spi, 1);
1220 ctlr->can_dma(ctlr, spi, t))
1221 count = omap2_mcspi_txrx_dma(spi, t);
1223 count = omap2_mcspi_txrx_pio(spi, t);
1231 omap2_mcspi_set_enable(spi, 0);
1234 omap2_mcspi_set_fifo(spi, t, 0);
1240 status = omap2_mcspi_setup_transfer(spi, NULL);
1248 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1251 omap2_mcspi_set_enable(spi, 0);
1253 if (spi_get_csgpiod(spi, 0))
1254 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1257 omap2_mcspi_set_fifo(spi, t, 0);
1275 if (msg->spi->controller_state == cs)
1290 struct spi_device *spi,
1293 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
1295 &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
1309 static size_t omap2_mcspi_max_xfer_size(struct spi_device *spi)
1311 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
1313 &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
1435 if (of_property_read_bool(node, "spi-slave"))
1442 /* the spi->mode bits understood by this driver: */
1466 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);