Lines Matching defs:mcspi
30 #include <linux/platform_data/spi-omap2-mcspi.h>
149 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
151 writel_relaxed(val, mcspi->base + idx);
156 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
158 return readl_relaxed(mcspi->base + idx);
240 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
251 int err = pm_runtime_resume_and_get(mcspi->dev);
253 dev_err(mcspi->dev, "failed to get sync: %d\n", err);
266 pm_runtime_mark_last_busy(mcspi->dev);
267 pm_runtime_put_autosuspend(mcspi->dev);
273 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
274 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
298 struct omap2_mcspi *mcspi;
303 mcspi = spi_controller_get_devdata(ctlr);
333 mcspi->fifo_depth = max_fifo_depth;
346 mcspi->fifo_depth = 0;
366 static int mcspi_wait_for_completion(struct omap2_mcspi *mcspi,
369 if (spi_controller_is_target(mcspi->ctlr)) {
371 mcspi->target_aborted)
383 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
384 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
395 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
396 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
408 struct omap2_mcspi *mcspi;
412 mcspi = spi_controller_get_devdata(spi->controller);
413 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
437 struct omap2_mcspi *mcspi;
450 mcspi = spi_controller_get_devdata(spi->controller);
451 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
459 if (mcspi->fifo_depth == 0)
479 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
518 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_rx_completion);
519 if (ret || mcspi->target_aborted) {
528 if (mcspi->fifo_depth > 0)
582 struct omap2_mcspi *mcspi;
595 mcspi = spi_controller_get_devdata(spi->controller);
596 mcspi_dma = &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
622 mcspi->target_aborted = false;
625 reinit_completion(&mcspi->txdone);
641 ret = mcspi_wait_for_completion(mcspi, &mcspi_dma->dma_tx_completion);
642 if (ret || mcspi->target_aborted) {
648 if (spi_controller_is_target(mcspi->ctlr)) {
649 ret = mcspi_wait_for_completion(mcspi, &mcspi->txdone);
650 if (ret || mcspi->target_aborted)
654 if (mcspi->fifo_depth > 0) {
655 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
661 mcspi_write_reg(mcspi->ctlr, OMAP2_MCSPI_IRQSTATUS,
668 if (mcspi->fifo_depth > 0) {
901 struct omap2_mcspi *mcspi;
906 mcspi = spi_controller_get_devdata(spi->controller);
916 ref_clk_hz = mcspi->ref_clk_hz;
935 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
994 static int omap2_mcspi_request_dma(struct omap2_mcspi *mcspi,
999 mcspi_dma->dma_rx = dma_request_chan(mcspi->dev,
1007 mcspi_dma->dma_tx = dma_request_chan(mcspi->dev,
1025 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
1030 mcspi_dma = &mcspi->dma_channels[i];
1060 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
1061 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1068 cs->base = mcspi->base + spi_get_chipselect(spi, 0) * 0x14;
1069 cs->phys = mcspi->phys + spi_get_chipselect(spi, 0) * 0x14;
1079 ret = pm_runtime_resume_and_get(mcspi->dev);
1091 pm_runtime_mark_last_busy(mcspi->dev);
1092 pm_runtime_put_autosuspend(mcspi->dev);
1099 struct omap2_mcspi *mcspi = data;
1102 irqstat = mcspi_read_reg(mcspi->ctlr, OMAP2_MCSPI_IRQSTATUS);
1107 mcspi_write_reg(mcspi->ctlr, OMAP2_MCSPI_IRQENABLE, 0);
1109 complete(&mcspi->txdone);
1116 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
1117 struct omap2_mcspi_dma *mcspi_dma = mcspi->dma_channels;
1119 mcspi->target_aborted = true;
1122 complete(&mcspi->txdone);
1139 struct omap2_mcspi *mcspi;
1147 mcspi = spi_controller_get_devdata(ctlr);
1148 mcspi_dma = mcspi->dma_channels + spi_get_chipselect(spi, 0);
1179 chconf = mcspi->ctx.modulctrl;
1182 mcspi->ctx.modulctrl =
1233 if (mcspi->fifo_depth > 0)
1244 chconf = mcspi->ctx.modulctrl;
1247 mcspi->ctx.modulctrl =
1256 if (mcspi->fifo_depth > 0 && t)
1265 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
1266 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1293 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
1295 &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
1311 struct omap2_mcspi *mcspi = spi_controller_get_devdata(spi->controller);
1313 &mcspi->dma_channels[spi_get_chipselect(spi, 0)];
1315 if (mcspi->max_xfer_len && mcspi_dma->dma_rx)
1316 return mcspi->max_xfer_len;
1321 static int omap2_mcspi_controller_setup(struct omap2_mcspi *mcspi)
1323 struct spi_controller *ctlr = mcspi->ctlr;
1324 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1327 ret = pm_runtime_resume_and_get(mcspi->dev);
1336 pm_runtime_mark_last_busy(mcspi->dev);
1337 pm_runtime_put_autosuspend(mcspi->dev);
1360 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
1361 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1409 .compatible = "ti,omap2-mcspi",
1413 .compatible = "ti,omap4-mcspi",
1417 .compatible = "ti,am654-mcspi",
1428 struct omap2_mcspi *mcspi;
1436 ctlr = spi_alloc_target(&pdev->dev, sizeof(*mcspi));
1438 ctlr = spi_alloc_host(&pdev->dev, sizeof(*mcspi));
1458 mcspi = spi_controller_get_devdata(ctlr);
1459 mcspi->ctlr = ctlr;
1469 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1473 mcspi->pin_dir = pdata->pin_dir;
1477 mcspi->max_xfer_len = pdata->max_xfer_len;
1481 mcspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
1482 if (IS_ERR(mcspi->base)) {
1483 status = PTR_ERR(mcspi->base);
1486 mcspi->phys = r->start + regs_offset;
1487 mcspi->base += regs_offset;
1489 mcspi->dev = &pdev->dev;
1491 INIT_LIST_HEAD(&mcspi->ctx.cs);
1493 mcspi->dma_channels = devm_kcalloc(&pdev->dev, ctlr->num_chipselect,
1496 if (mcspi->dma_channels == NULL) {
1502 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1503 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1505 status = omap2_mcspi_request_dma(mcspi,
1506 &mcspi->dma_channels[i]);
1514 init_completion(&mcspi->txdone);
1517 mcspi);
1523 mcspi->ref_clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
1524 if (mcspi->ref_clk)
1525 mcspi->ref_clk_hz = clk_get_rate(mcspi->ref_clk);
1527 mcspi->ref_clk_hz = OMAP2_MCSPI_MAX_FREQ;
1528 ctlr->max_speed_hz = mcspi->ref_clk_hz;
1529 ctlr->min_speed_hz = mcspi->ref_clk_hz >> 15;
1535 status = omap2_mcspi_controller_setup(mcspi);
1558 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
1562 pm_runtime_dont_use_autosuspend(mcspi->dev);
1563 pm_runtime_put_sync(mcspi->dev);
1573 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
1578 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
1583 dev_warn(mcspi->dev, "%s: controller suspend failed: %i\n",
1592 struct omap2_mcspi *mcspi = spi_controller_get_devdata(ctlr);
1597 dev_warn(mcspi->dev, "%s: controller resume failed: %i\n",