Lines Matching defs:fiu
241 struct npcm_fiu_spi *fiu;
265 static void npcm_fiu_set_drd(struct npcm_fiu_spi *fiu,
268 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
272 fiu->drd_op.addr.buswidth = op->addr.buswidth;
273 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
276 fiu->drd_op.dummy.nbytes = op->dummy.nbytes;
277 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
279 fiu->drd_op.cmd.opcode = op->cmd.opcode;
280 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
283 fiu->drd_op.addr.nbytes = op->addr.nbytes;
289 struct npcm_fiu_spi *fiu =
291 struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(desc->mem->spi, 0)];
297 if (fiu->spix_mode) {
301 if (desc->info.op_tmpl.addr.buswidth != fiu->drd_op.addr.buswidth ||
302 desc->info.op_tmpl.dummy.nbytes != fiu->drd_op.dummy.nbytes ||
303 desc->info.op_tmpl.cmd.opcode != fiu->drd_op.cmd.opcode ||
304 desc->info.op_tmpl.addr.nbytes != fiu->drd_op.addr.nbytes)
305 npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);
316 struct npcm_fiu_spi *fiu =
318 struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(desc->mem->spi, 0)];
324 if (fiu->spix_mode)
337 struct npcm_fiu_spi *fiu =
345 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
349 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,
363 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, addr);
365 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0);
369 regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg);
370 regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
373 ret = regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val,
381 regmap_read(fiu->regmap, NPCM_FIU_UMA_DR0 + (i * 4),
393 struct npcm_fiu_spi *fiu =
400 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
405 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,
411 regmap_write(fiu->regmap, NPCM_FIU_UMA_DW0 + (i * 4),
422 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, op->addr.val);
424 regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0);
428 regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg);
430 regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
434 return regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val,
442 struct npcm_fiu_spi *fiu =
453 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
457 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
482 regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
519 static void npcm_fiux_set_direct_wr(struct npcm_fiu_spi *fiu)
521 regmap_write(fiu->regmap, NPCM_FIU_DWR_CFG,
523 regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG,
526 regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG,
531 static void npcm_fiux_set_direct_rd(struct npcm_fiu_spi *fiu)
535 regmap_write(fiu->regmap, NPCM_FIU_DRD_CFG,
537 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
540 regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
547 struct npcm_fiu_spi *fiu =
549 struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(mem->spi, 0)];
553 dev_dbg(fiu->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
558 if (fiu->spix_mode || op->addr.nbytes > 4)
561 if (fiu->clkrate != chip->clkrate) {
562 ret = clk_set_rate(fiu->clk, chip->clkrate);
564 dev_warn(fiu->dev, "Failed setting %lu frequency, stay at %lu frequency\n",
565 chip->clkrate, fiu->clkrate);
567 fiu->clkrate = chip->clkrate;
607 struct npcm_fiu_spi *fiu =
609 struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(desc->mem->spi, 0)];
612 if (!fiu->res_mem) {
613 dev_warn(fiu->dev, "Reserved memory not defined, direct read disabled\n");
618 if (!fiu->spix_mode &&
626 devm_ioremap(fiu->dev, (fiu->res_mem->start +
627 (fiu->info->max_map_size *
631 dev_warn(fiu->dev, "Error mapping memory region, direct read disabled\n");
637 if (of_device_is_compatible(fiu->dev->of_node, "nuvoton,npcm750-fiu")) {
641 dev_warn(fiu->dev, "Didn't find nuvoton,npcm750-gcr, direct read disabled\n");
649 regmap_update_bits(fiu->regmap, NPCM_FIU_CFG,
655 if (!fiu->spix_mode)
656 npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);
658 npcm_fiux_set_direct_rd(fiu);
661 npcm_fiux_set_direct_wr(fiu);
670 struct npcm_fiu_spi *fiu = spi_controller_get_devdata(ctrl);
673 chip = &fiu->chip[spi_get_chipselect(spi, 0)];
674 chip->fiu = fiu;
678 fiu->clkrate = clk_get_rate(fiu->clk);
691 { .compatible = "nuvoton,npcm750-fiu", .data = &npcm7xx_fiu_data },
692 { .compatible = "nuvoton,npcm845-fiu", .data = &npxm8xx_fiu_data },
701 struct npcm_fiu_spi *fiu;
705 ctrl = devm_spi_alloc_host(dev, sizeof(*fiu));
709 fiu = spi_controller_get_devdata(ctrl);
717 id = of_alias_get_id(dev->of_node, "fiu");
723 fiu->info = &fiu_data_match->npcm_fiu_data_info[id];
725 platform_set_drvdata(pdev, fiu);
726 fiu->dev = dev;
732 fiu->regmap = devm_regmap_init_mmio(dev, regbase,
734 if (IS_ERR(fiu->regmap)) {
736 return PTR_ERR(fiu->regmap);
739 fiu->res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
741 fiu->clk = devm_clk_get(dev, NULL);
742 if (IS_ERR(fiu->clk))
743 return PTR_ERR(fiu->clk);
745 fiu->spix_mode = of_property_read_bool(dev->of_node,
748 platform_set_drvdata(pdev, fiu);
749 clk_prepare_enable(fiu->clk);
756 ctrl->num_chipselect = fiu->info->max_cs;
761 clk_disable_unprepare(fiu->clk);
768 struct npcm_fiu_spi *fiu = platform_get_drvdata(pdev);
770 clk_disable_unprepare(fiu->clk);