Lines Matching refs:mxic
6 // Mason Yang <masonccyang@mxic.com.tw>
7 // zhengxunli <zhengxunli@mxic.com.tw>
16 #include <linux/mtd/nand-ecc-mxic.h>
191 static int mxic_spi_clk_enable(struct mxic_spi *mxic)
195 ret = clk_prepare_enable(mxic->send_clk);
199 ret = clk_prepare_enable(mxic->send_dly_clk);
206 clk_disable_unprepare(mxic->send_clk);
211 static void mxic_spi_clk_disable(struct mxic_spi *mxic)
213 clk_disable_unprepare(mxic->send_clk);
214 clk_disable_unprepare(mxic->send_dly_clk);
217 static void mxic_spi_set_input_delay_dqs(struct mxic_spi *mxic, u8 idly_code)
223 mxic->regs + IDLY_CODE(0));
228 mxic->regs + IDLY_CODE(1));
231 static int mxic_spi_clk_setup(struct mxic_spi *mxic, unsigned long freq)
235 ret = clk_set_rate(mxic->send_clk, freq);
239 ret = clk_set_rate(mxic->send_dly_clk, freq);
247 mxic_spi_set_input_delay_dqs(mxic, 0xf);
257 ret = clk_set_phase(mxic->send_dly_clk, 9 * freq / 25000000);
264 static int mxic_spi_set_freq(struct mxic_spi *mxic, unsigned long freq)
268 if (mxic->cur_speed_hz == freq)
271 mxic_spi_clk_disable(mxic);
272 ret = mxic_spi_clk_setup(mxic, freq);
276 ret = mxic_spi_clk_enable(mxic);
280 mxic->cur_speed_hz = freq;
285 static void mxic_spi_hw_init(struct mxic_spi *mxic)
287 writel(0, mxic->regs + DATA_STROB);
288 writel(INT_STS_ALL, mxic->regs + INT_STS_EN);
289 writel(0, mxic->regs + HC_EN);
290 writel(0, mxic->regs + LRD_CFG);
291 writel(0, mxic->regs + LRD_CTRL);
294 mxic->regs + HC_CFG);
342 static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
359 ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
364 writel(data, mxic->regs + TXD(nbytes % 4));
366 ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
371 ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
377 data = readl(mxic->regs + RXD);
382 WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
393 struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master);
400 writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);
403 mxic->regs + LRD_CFG);
404 writel(desc->info.offset + offs, mxic->regs + LRD_ADDR);
405 len = min_t(size_t, len, mxic->linear.size);
406 writel(len, mxic->regs + LRD_RANGE);
410 mxic->regs + LRD_CTRL);
412 if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) {
413 ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine,
415 mxic->linear.dma + offs);
419 memcpy_fromio(buf, mxic->linear.map, len);
422 writel(INT_LRD_DIS, mxic->regs + INT_STS);
423 writel(0, mxic->regs + LRD_CTRL);
425 ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
437 struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master);
444 writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);
447 mxic->regs + LWR_CFG);
448 writel(desc->info.offset + offs, mxic->regs + LWR_ADDR);
449 len = min_t(size_t, len, mxic->linear.size);
450 writel(len, mxic->regs + LWR_RANGE);
454 mxic->regs + LWR_CTRL);
456 if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) {
457 ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine,
459 mxic->linear.dma + offs);
463 memcpy_toio(mxic->linear.map, buf, len);
466 writel(INT_LWR_DIS, mxic->regs + INT_STS);
467 writel(0, mxic->regs + LWR_CTRL);
469 ret = readl_poll_timeout(mxic->regs + INT_STS, sts,
496 struct mxic_spi *mxic = spi_master_get_devdata(desc->mem->spi->master);
498 if (!mxic->linear.map)
513 struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master);
517 ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
522 mxic->regs + HC_CFG);
524 writel(HC_EN_BIT, mxic->regs + HC_EN);
527 mxic->regs + SS_CTRL(spi_get_chipselect(mem->spi, 0)));
529 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
530 mxic->regs + HC_CFG);
535 ret = mxic_spi_data_xfer(mxic, cmd, NULL, op->cmd.nbytes);
542 ret = mxic_spi_data_xfer(mxic, addr, NULL, op->addr.nbytes);
546 ret = mxic_spi_data_xfer(mxic, NULL, NULL, op->dummy.nbytes);
550 ret = mxic_spi_data_xfer(mxic,
558 writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
559 mxic->regs + HC_CFG);
560 writel(0, mxic->regs + HC_EN);
580 struct mxic_spi *mxic = spi_master_get_devdata(spi->master);
583 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_EN,
584 mxic->regs + HC_CFG);
585 writel(HC_EN_BIT, mxic->regs + HC_EN);
586 writel(readl(mxic->regs + HC_CFG) | HC_CFG_MAN_CS_ASSERT,
587 mxic->regs + HC_CFG);
589 writel(readl(mxic->regs + HC_CFG) & ~HC_CFG_MAN_CS_ASSERT,
590 mxic->regs + HC_CFG);
591 writel(0, mxic->regs + HC_EN);
599 struct mxic_spi *mxic = spi_master_get_devdata(master);
611 ret = mxic_spi_set_freq(mxic, t->speed_hz);
629 mxic->regs + SS_CTRL(0));
631 ret = mxic_spi_data_xfer(mxic, t->tx_buf, t->rx_buf, t->len);
644 struct mxic_spi *mxic = nand->ecc.engine->priv;
646 mxic->ecc.use_pipelined_conf = true;
654 struct mxic_spi *mxic = nand->ecc.engine->priv;
656 mxic->ecc.use_pipelined_conf = false;
684 static void mxic_spi_mem_ecc_remove(struct mxic_spi *mxic)
686 if (mxic->ecc.pipelined_engine) {
687 mxic_ecc_put_pipelined_engine(mxic->ecc.pipelined_engine);
688 nand_ecc_unregister_on_host_hw_engine(mxic->ecc.pipelined_engine);
693 struct mxic_spi *mxic)
707 eng->priv = mxic;
708 mxic->ecc.pipelined_engine = eng;
717 struct mxic_spi *mxic = spi_master_get_devdata(master);
719 mxic_spi_clk_disable(mxic);
720 clk_disable_unprepare(mxic->ps_clk);
728 struct mxic_spi *mxic = spi_master_get_devdata(master);
731 ret = clk_prepare_enable(mxic->ps_clk);
737 return mxic_spi_clk_enable(mxic);
749 struct mxic_spi *mxic;
758 mxic = spi_master_get_devdata(master);
759 mxic->dev = &pdev->dev;
763 mxic->ps_clk = devm_clk_get(&pdev->dev, "ps_clk");
764 if (IS_ERR(mxic->ps_clk))
765 return PTR_ERR(mxic->ps_clk);
767 mxic->send_clk = devm_clk_get(&pdev->dev, "send_clk");
768 if (IS_ERR(mxic->send_clk))
769 return PTR_ERR(mxic->send_clk);
771 mxic->send_dly_clk = devm_clk_get(&pdev->dev, "send_dly_clk");
772 if (IS_ERR(mxic->send_dly_clk))
773 return PTR_ERR(mxic->send_dly_clk);
775 mxic->regs = devm_platform_ioremap_resource_byname(pdev, "regs");
776 if (IS_ERR(mxic->regs))
777 return PTR_ERR(mxic->regs);
780 mxic->linear.map = devm_ioremap_resource(&pdev->dev, res);
781 if (!IS_ERR(mxic->linear.map)) {
782 mxic->linear.dma = res->start;
783 mxic->linear.size = resource_size(res);
785 mxic->linear.map = NULL;
803 mxic_spi_hw_init(mxic);
805 ret = mxic_spi_mem_ecc_probe(pdev, mxic);
815 mxic_spi_mem_ecc_remove(mxic);
824 struct mxic_spi *mxic = spi_master_get_devdata(master);
827 mxic_spi_mem_ecc_remove(mxic);
841 .name = "mxic-spi",
848 MODULE_AUTHOR("Mason Yang <masonccyang@mxic.com.tw>");