Lines Matching defs:qspi
103 * struct mchp_coreqspi - Defines qspi driver instance
126 static int mchp_coreqspi_set_mode(struct mchp_coreqspi *qspi, const struct spi_mem_op *op)
128 u32 control = readl_relaxed(qspi->regs + REG_CONTROL);
156 writel_relaxed(control, qspi->regs + REG_CONTROL);
161 static inline void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi)
165 if (!qspi->rx_len)
168 control = readl_relaxed(qspi->regs + REG_CONTROL);
175 writel_relaxed(control, qspi->regs + REG_CONTROL);
177 while (qspi->rx_len >= 4) {
178 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY)
180 data = readl_relaxed(qspi->regs + REG_X4_RX_DATA);
181 *(u32 *)qspi->rxbuf = data;
182 qspi->rxbuf += 4;
183 qspi->rx_len -= 4;
187 writel_relaxed(control, qspi->regs + REG_CONTROL);
189 while (qspi->rx_len--) {
190 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY)
192 data = readl_relaxed(qspi->regs + REG_RX_DATA);
193 *qspi->rxbuf++ = (data & 0xFF);
197 static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi, bool word)
201 control = readl_relaxed(qspi->regs + REG_CONTROL);
203 writel_relaxed(control, qspi->regs + REG_CONTROL);
205 while (qspi->tx_len >= 4) {
206 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
208 data = *(u32 *)qspi->txbuf;
209 qspi->txbuf += 4;
210 qspi->tx_len -= 4;
211 writel_relaxed(data, qspi->regs + REG_X4_TX_DATA);
215 writel_relaxed(control, qspi->regs + REG_CONTROL);
217 while (qspi->tx_len--) {
218 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL)
220 data = *qspi->txbuf++;
221 writel_relaxed(data, qspi->regs + REG_TX_DATA);
225 static void mchp_coreqspi_enable_ints(struct mchp_coreqspi *qspi)
231 writel_relaxed(mask, qspi->regs + REG_IEN);
234 static void mchp_coreqspi_disable_ints(struct mchp_coreqspi *qspi)
236 writel_relaxed(0, qspi->regs + REG_IEN);
241 struct mchp_coreqspi *qspi = (struct mchp_coreqspi *)dev_id;
243 int intfield = readl_relaxed(qspi->regs + REG_STATUS) & STATUS_MASK;
249 writel_relaxed(IEN_TXDONE, qspi->regs + REG_STATUS);
254 writel_relaxed(IEN_RXAVAILABLE, qspi->regs + REG_STATUS);
255 mchp_coreqspi_read_op(qspi);
260 writel_relaxed(IEN_RXDONE, qspi->regs + REG_STATUS);
261 complete(&qspi->data_completion);
268 static int mchp_coreqspi_setup_clock(struct mchp_coreqspi *qspi, struct spi_device *spi)
273 clk_hz = clk_get_rate(qspi->clk);
285 control = readl_relaxed(qspi->regs + REG_CONTROL);
287 writel_relaxed(control, qspi->regs + REG_CONTROL);
288 control = readl_relaxed(qspi->regs + REG_CONTROL);
295 writel_relaxed(control, qspi->regs + REG_CONTROL);
303 struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr);
304 u32 control = readl_relaxed(qspi->regs + REG_CONTROL);
308 writel_relaxed(control, qspi->regs + REG_CONTROL);
313 static inline void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi, const struct spi_mem_op *op)
351 writel_relaxed(frames, qspi->regs + REG_FRAMESUP);
359 ctrl = readl_relaxed(qspi->regs + REG_CONTROL);
365 writel_relaxed(frames, qspi->regs + REG_FRAMES);
370 struct mchp_coreqspi *qspi = spi_controller_get_devdata
375 ret = readl_poll_timeout(qspi->regs + REG_STATUS, status,
389 struct mchp_coreqspi *qspi = spi_controller_get_devdata
396 mutex_lock(&qspi->op_lock);
401 err = mchp_coreqspi_setup_clock(qspi, mem->spi);
405 err = mchp_coreqspi_set_mode(qspi, op);
409 reinit_completion(&qspi->data_completion);
410 mchp_coreqspi_config_op(qspi, op);
412 qspi->txbuf = &opcode;
413 qspi->rxbuf = NULL;
414 qspi->tx_len = op->cmd.nbytes;
415 qspi->rx_len = 0;
416 mchp_coreqspi_write_op(qspi, false);
419 qspi->txbuf = &opaddr[0];
422 qspi->txbuf[i] = address >> (8 * (op->addr.nbytes - i - 1));
424 qspi->rxbuf = NULL;
425 qspi->tx_len = op->addr.nbytes;
426 qspi->rx_len = 0;
427 mchp_coreqspi_write_op(qspi, false);
432 qspi->txbuf = (u8 *)op->data.buf.out;
433 qspi->rxbuf = NULL;
434 qspi->rx_len = 0;
435 qspi->tx_len = op->data.nbytes;
436 mchp_coreqspi_write_op(qspi, true);
438 qspi->txbuf = NULL;
439 qspi->rxbuf = (u8 *)op->data.buf.in;
440 qspi->rx_len = op->data.nbytes;
441 qspi->tx_len = 0;
445 mchp_coreqspi_enable_ints(qspi);
447 if (!wait_for_completion_timeout(&qspi->data_completion, msecs_to_jiffies(1000)))
451 mutex_unlock(&qspi->op_lock);
452 mchp_coreqspi_disable_ints(qspi);
503 struct mchp_coreqspi *qspi;
508 ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*qspi));
513 qspi = spi_controller_get_devdata(ctlr);
514 platform_set_drvdata(pdev, qspi);
516 qspi->regs = devm_platform_ioremap_resource(pdev, 0);
517 if (IS_ERR(qspi->regs))
518 return dev_err_probe(&pdev->dev, PTR_ERR(qspi->regs),
521 qspi->clk = devm_clk_get(&pdev->dev, NULL);
522 if (IS_ERR(qspi->clk))
523 return dev_err_probe(&pdev->dev, PTR_ERR(qspi->clk),
526 ret = clk_prepare_enable(qspi->clk);
531 init_completion(&qspi->data_completion);
532 mutex_init(&qspi->op_lock);
534 qspi->irq = platform_get_irq(pdev, 0);
535 if (qspi->irq < 0) {
536 ret = qspi->irq;
540 ret = devm_request_irq(&pdev->dev, qspi->irq, mchp_coreqspi_isr,
541 IRQF_SHARED, pdev->name, qspi);
564 clk_disable_unprepare(qspi->clk);
571 struct mchp_coreqspi *qspi = platform_get_drvdata(pdev);
572 u32 control = readl_relaxed(qspi->regs + REG_CONTROL);
574 mchp_coreqspi_disable_ints(qspi);
576 writel_relaxed(control, qspi->regs + REG_CONTROL);
577 clk_disable_unprepare(qspi->clk);