Lines Matching refs:init
628 struct clk_init_data init;
633 memset(&init, 0, sizeof(init));
636 init.parent_data = parent_data;
645 init.name = name;
646 init.ops = &clk_fixed_factor_ops;
647 init.flags = 0;
652 init.num_parents = 1;
656 pow2_fixed_div->hw.init = &init;
663 init.name = name;
664 init.ops = &meson_spicc_pow2_clk_ops;
669 init.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
671 init.num_parents = 1;
677 spicc->pow2_div.hw.init = &init;
692 struct clk_init_data init;
697 memset(&init, 0, sizeof(init));
700 init.parent_data = parent_data;
709 init.name = name;
710 init.ops = &clk_fixed_factor_ops;
711 init.flags = 0;
716 init.num_parents = 1;
720 enh_fixed_div->hw.init = &init;
731 init.name = name;
732 init.ops = &clk_divider_ops;
733 init.flags = CLK_SET_RATE_PARENT;
735 init.num_parents = 1;
740 enh_div->hw.init = &init;
751 init.name = name;
752 init.ops = &clk_mux_ops;
755 init.num_parents = 2;
756 init.flags = CLK_SET_RATE_PARENT;
761 mux->hw.init = &init;