Lines Matching refs:spi
20 #include <linux/spi/spi.h>
156 int (*cfg_irq)(struct platform_device *pdev, struct lantiq_ssc_spi *spi);
189 static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg)
191 return __raw_readl(spi->regbase + reg);
194 static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val,
197 __raw_writel(val, spi->regbase + reg);
200 static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,
203 u32 val = __raw_readl(spi->regbase + reg);
207 __raw_writel(val, spi->regbase + reg);
210 static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
212 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
213 u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
218 static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
220 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
221 u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
226 static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
228 return spi->tx_fifo_size - tx_fifo_level(spi);
231 static void rx_fifo_reset(const struct lantiq_ssc_spi *spi)
233 u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S;
236 lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON);
239 static void tx_fifo_reset(const struct lantiq_ssc_spi *spi)
244 lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON);
247 static void rx_fifo_flush(const struct lantiq_ssc_spi *spi)
249 lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
252 static void tx_fifo_flush(const struct lantiq_ssc_spi *spi)
254 lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
257 static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi)
259 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
262 static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi)
264 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
267 static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi,
280 spi_clk = clk_get_rate(spi->fpi_clk) / 2;
290 dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n",
293 lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT);
296 static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi,
304 lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON);
307 static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi,
342 lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON);
345 static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)
347 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
353 lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC);
356 hw_enter_config_mode(spi);
359 lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
362 lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
367 hw_setup_bits_per_word(spi, spi->bits_per_word);
368 hw_setup_clock_mode(spi, SPI_MODE_0);
371 lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS |
376 lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON);
377 lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO);
380 rx_fifo_reset(spi);
381 tx_fifo_reset(spi);
384 lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r |
391 struct lantiq_ssc_spi *spi = spi_controller_get_devdata(host);
399 dev_dbg(spi->dev, "using internal chipselect %u\n", cs);
401 if (cs < spi->base_cs) {
402 dev_err(spi->dev,
403 "chipselect %i too small (min %i)\n", cs, spi->base_cs);
408 gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S);
412 gpocon |= 1 << (cs - spi->base_cs);
414 lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON);
422 struct lantiq_ssc_spi *spi = spi_controller_get_devdata(host);
424 hw_enter_config_mode(spi);
425 hw_setup_clock_mode(spi, message->spi->mode);
426 hw_enter_active_mode(spi);
431 static void hw_setup_transfer(struct lantiq_ssc_spi *spi,
438 if (bits_per_word != spi->bits_per_word ||
439 speed_hz != spi->speed_hz) {
440 hw_enter_config_mode(spi);
441 hw_setup_speed_hz(spi, speed_hz);
442 hw_setup_bits_per_word(spi, bits_per_word);
443 hw_enter_active_mode(spi);
445 spi->speed_hz = speed_hz;
446 spi->bits_per_word = bits_per_word;
450 con = lantiq_ssc_readl(spi, LTQ_SPI_CON);
461 lantiq_ssc_writel(spi, con, LTQ_SPI_CON);
467 struct lantiq_ssc_spi *spi = spi_controller_get_devdata(host);
469 flush_workqueue(spi->wq);
472 lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF,
478 static void tx_fifo_write(struct lantiq_ssc_spi *spi)
484 unsigned int tx_free = tx_fifo_free(spi);
486 spi->fdx_tx_level = 0;
487 while (spi->tx_todo && tx_free) {
488 switch (spi->bits_per_word) {
490 tx8 = spi->tx;
492 spi->tx_todo--;
493 spi->tx++;
496 tx16 = (u16 *) spi->tx;
498 spi->tx_todo -= 2;
499 spi->tx += 2;
502 tx32 = (u32 *) spi->tx;
504 spi->tx_todo -= 4;
505 spi->tx += 4;
513 lantiq_ssc_writel(spi, data, LTQ_SPI_TB);
515 spi->fdx_tx_level++;
519 static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi)
525 unsigned int rx_fill = rx_fifo_level(spi);
531 while (rx_fill != spi->fdx_tx_level)
532 rx_fill = rx_fifo_level(spi);
535 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
537 switch (spi->bits_per_word) {
539 rx8 = spi->rx;
541 spi->rx_todo--;
542 spi->rx++;
545 rx16 = (u16 *) spi->rx;
547 spi->rx_todo -= 2;
548 spi->rx += 2;
551 rx32 = (u32 *) spi->rx;
553 spi->rx_todo -= 4;
554 spi->rx += 4;
565 static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi)
570 unsigned int rx_fill = rx_fifo_level(spi);
580 if (spi->rx_todo < 4) {
581 rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) &
583 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
586 rx8 = spi->rx;
592 spi->rx_todo--;
593 spi->rx++;
596 data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
597 rx32 = (u32 *) spi->rx;
600 spi->rx_todo -= 4;
601 spi->rx += 4;
607 static void rx_request(struct lantiq_ssc_spi *spi)
616 rxreq = spi->rx_todo;
617 rxreq_max = spi->rx_fifo_size * 4;
621 lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ);
626 struct lantiq_ssc_spi *spi = data;
627 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
628 u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
630 spin_lock(&spi->lock);
632 lantiq_ssc_writel(spi, val, hwcfg->irncr);
634 if (spi->tx) {
635 if (spi->rx && spi->rx_todo)
636 rx_fifo_read_full_duplex(spi);
638 if (spi->tx_todo)
639 tx_fifo_write(spi);
640 else if (!tx_fifo_level(spi))
642 } else if (spi->rx) {
643 if (spi->rx_todo) {
644 rx_fifo_read_half_duplex(spi);
646 if (spi->rx_todo)
647 rx_request(spi);
655 spin_unlock(&spi->lock);
659 queue_work(spi->wq, &spi->work);
660 spin_unlock(&spi->lock);
667 struct lantiq_ssc_spi *spi = data;
668 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
669 u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
670 u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
675 spin_lock(&spi->lock);
677 lantiq_ssc_writel(spi, val, hwcfg->irncr);
680 dev_err(spi->dev, "receive underflow error\n");
682 dev_err(spi->dev, "transmit underflow error\n");
684 dev_err(spi->dev, "abort error\n");
686 dev_err(spi->dev, "receive overflow error\n");
688 dev_err(spi->dev, "transmit overflow error\n");
690 dev_err(spi->dev, "mode error\n");
693 lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
696 if (spi->host->cur_msg)
697 spi->host->cur_msg->status = -EIO;
698 queue_work(spi->wq, &spi->work);
699 spin_unlock(&spi->lock);
706 struct lantiq_ssc_spi *spi = data;
707 const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
708 u32 val = lantiq_ssc_readl(spi, hwcfg->irncr);
722 static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev,
727 spin_lock_irqsave(&spi->lock, flags);
729 spi->tx = t->tx_buf;
730 spi->rx = t->rx_buf;
733 spi->tx_todo = t->len;
736 tx_fifo_write(spi);
739 if (spi->rx) {
740 spi->rx_todo = t->len;
743 if (!spi->tx)
744 rx_request(spi);
747 spin_unlock_irqrestore(&spi->lock, flags);
761 struct lantiq_ssc_spi *spi;
765 spi = container_of(work, typeof(*spi), work);
767 do_div(timeout, spi->speed_hz);
772 u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
775 spi_finalize_current_transfer(spi->host);
782 if (spi->host->cur_msg)
783 spi->host->cur_msg->status = -EIO;
784 spi_finalize_current_transfer(spi->host);
790 struct lantiq_ssc_spi *spi = spi_controller_get_devdata(host);
793 rx_fifo_flush(spi);
794 tx_fifo_flush(spi);
799 struct lantiq_ssc_spi *spi = spi_controller_get_devdata(spidev->controller);
804 fgpo = (1 << (cs - spi->base_cs));
806 fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S));
808 lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO);
815 struct lantiq_ssc_spi *spi = spi_controller_get_devdata(host);
817 hw_setup_transfer(spi, spidev, t);
819 return transfer_start(spi, spidev, t);
822 static int intel_lgm_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi)
830 return devm_request_irq(&pdev->dev, irq, intel_lgm_ssc_isr, 0, "spi", spi);
833 static int lantiq_cfg_irq(struct platform_device *pdev, struct lantiq_ssc_spi *spi)
842 0, LTQ_SPI_RX_IRQ_NAME, spi);
851 0, LTQ_SPI_TX_IRQ_NAME, spi);
861 0, LTQ_SPI_ERR_IRQ_NAME, spi);
896 { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
897 { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
898 { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
899 { .compatible = "intel,lgm-spi", .data = &intel_ssc_lgm, },
908 struct lantiq_ssc_spi *spi;
920 spi = spi_controller_get_devdata(host);
921 spi->host = host;
922 spi->dev = dev;
923 spi->hwcfg = hwcfg;
924 platform_set_drvdata(pdev, spi);
925 spi->regbase = devm_platform_ioremap_resource(pdev, 0);
926 if (IS_ERR(spi->regbase)) {
927 err = PTR_ERR(spi->regbase);
931 err = hwcfg->cfg_irq(pdev, spi);
935 spi->spi_clk = devm_clk_get(dev, "gate");
936 if (IS_ERR(spi->spi_clk)) {
937 err = PTR_ERR(spi->spi_clk);
940 err = clk_prepare_enable(spi->spi_clk);
949 spi->fpi_clk = clk_get_fpi();
951 spi->fpi_clk = clk_get(dev, "freq");
953 if (IS_ERR(spi->fpi_clk)) {
954 err = PTR_ERR(spi->fpi_clk);
961 spi->base_cs = 1;
962 of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs);
964 spin_lock_init(&spi->lock);
965 spi->bits_per_word = 8;
966 spi->speed_hz = 0;
982 spi->wq = alloc_ordered_workqueue(dev_name(dev), WQ_MEM_RECLAIM);
983 if (!spi->wq) {
987 INIT_WORK(&spi->work, lantiq_ssc_bussy_work);
989 id = lantiq_ssc_readl(spi, LTQ_SPI_ID);
990 spi->tx_fifo_size = (id >> LTQ_SPI_ID_TXFS_S) & hwcfg->fifo_size_mask;
991 spi->rx_fifo_size = (id >> LTQ_SPI_ID_RXFS_S) & hwcfg->fifo_size_mask;
995 lantiq_ssc_hw_init(spi);
999 revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma);
1003 dev_err(dev, "failed to register spi host\n");
1010 destroy_workqueue(spi->wq);
1012 clk_put(spi->fpi_clk);
1014 clk_disable_unprepare(spi->spi_clk);
1023 struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev);
1025 lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN);
1026 lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC);
1027 rx_fifo_flush(spi);
1028 tx_fifo_flush(spi);
1029 hw_enter_config_mode(spi);
1031 destroy_workqueue(spi->wq);
1032 clk_disable_unprepare(spi->spi_clk);
1033 clk_put(spi->fpi_clk);
1040 .name = "spi-lantiq-ssc",
1050 MODULE_ALIAS("platform:spi-lantiq-ssc");