Lines Matching defs:mode
54 #define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
56 #define LTQ_SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */
71 #define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
109 #define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
110 #define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
115 #define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
116 #define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
308 unsigned int mode)
313 * SPI mode mapping in CON register:
320 if (mode & SPI_CPHA)
325 if (mode & SPI_CPOL)
331 if (mode & SPI_LSB_FIRST)
336 /* Set loopback mode */
337 if (mode & SPI_LOOP)
350 * Set clock divider for run mode to 1 to
355 /* Put controller into config mode */
366 /* Setup default SPI mode */
370 /* Enable host mode and clear error flags */
407 /* set GPO pin to CS mode */
411 if (spidev->mode & SPI_CS_HIGH)
425 hw_setup_clock_mode(spi, message->spi->mode);
573 * In RX-only mode the bits per word value is ignored by HW. A value
690 dev_err(spi->dev, "mode error\n");
742 /* start shift clock in RX-only mode */
803 if (!!(spidev->mode & SPI_CS_HIGH) == enable)