Lines Matching refs:ispi
21 /* Offsets are from @ispi->base */
60 /* Offset is from @ispi->pregs */
68 /* Offsets are from @ispi->sregs */
179 int (*exec_op)(struct intel_spi *ispi,
189 static void intel_spi_dump_regs(struct intel_spi *ispi)
194 dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));
196 value = readl(ispi->base + HSFSTS_CTL);
197 dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);
199 dev_dbg(ispi->dev, "-> Locked\n");
201 dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));
202 dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));
205 dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",
206 i, readl(ispi->base + FDATA(i)));
208 dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));
210 for (i = 0; i < ispi->nregions; i++)
211 dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,
212 readl(ispi->base + FREG(i)));
213 for (i = 0; i < ispi->pr_num; i++)
214 dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,
215 readl(ispi->pregs + PR(i)));
217 if (ispi->sregs) {
218 value = readl(ispi->sregs + SSFSTS_CTL);
219 dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);
220 dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",
221 readl(ispi->sregs + PREOP_OPTYPE));
222 dev_dbg(ispi->dev, "OPMENU0=0x%08x\n",
223 readl(ispi->sregs + OPMENU0));
224 dev_dbg(ispi->dev, "OPMENU1=0x%08x\n",
225 readl(ispi->sregs + OPMENU1));
228 dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC));
229 dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC));
231 dev_dbg(ispi->dev, "Protected regions:\n");
232 for (i = 0; i < ispi->pr_num; i++) {
235 value = readl(ispi->pregs + PR(i));
242 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",
247 dev_dbg(ispi->dev, "Flash regions:\n");
248 for (i = 0; i < ispi->nregions; i++) {
251 region = readl(ispi->base + FREG(i));
256 dev_dbg(ispi->dev, " %02d disabled\n", i);
258 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",
262 dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",
263 ispi->swseq_reg ? 'S' : 'H');
264 dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n",
265 ispi->swseq_erase ? 'S' : 'H');
269 static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size)
279 memcpy_fromio(buf, ispi->base + FDATA(i), bytes);
289 static int intel_spi_write_block(struct intel_spi *ispi, const void *buf,
300 memcpy_toio(ispi->base + FDATA(i), buf, bytes);
309 static int intel_spi_wait_hw_busy(struct intel_spi *ispi)
313 return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,
318 static int intel_spi_wait_sw_busy(struct intel_spi *ispi)
322 return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,
327 static bool intel_spi_set_writeable(struct intel_spi *ispi)
329 if (!ispi->info->set_writeable)
332 return ispi->info->set_writeable(ispi->base, ispi->info->data);
335 static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype)
340 if (ispi->locked) {
341 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)
342 if (ispi->opcodes[i] == opcode)
349 writel(opcode, ispi->sregs + OPMENU0);
350 preop = readw(ispi->sregs + PREOP_OPTYPE);
351 writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);
356 static int intel_spi_hw_cycle(struct intel_spi *ispi,
365 val = readl(ispi->base + HSFSTS_CTL);
371 writel(val, ispi->base + HSFSTS_CTL);
373 ret = intel_spi_wait_hw_busy(ispi);
377 status = readl(ispi->base + HSFSTS_CTL);
386 static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len,
393 ret = intel_spi_opcode_index(ispi, opcode, optype);
401 atomic_preopcode = ispi->atomic_preopcode;
402 ispi->atomic_preopcode = 0;
417 preop = readw(ispi->sregs + PREOP_OPTYPE);
433 writel(val, ispi->sregs + SSFSTS_CTL);
435 ret = intel_spi_wait_sw_busy(ispi);
439 status = readl(ispi->sregs + SSFSTS_CTL);
448 static u32 intel_spi_chip_addr(const struct intel_spi *ispi,
454 return (spi_get_chipselect(mem->spi, 0) == 1) ? ispi->chip0_size : 0;
457 static int intel_spi_read_reg(struct intel_spi *ispi, const struct spi_mem *mem,
461 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;
466 writel(addr, ispi->base + FADDR);
468 if (ispi->swseq_reg)
469 ret = intel_spi_sw_cycle(ispi, opcode, nbytes,
472 ret = intel_spi_hw_cycle(ispi, iop, nbytes);
477 return intel_spi_read_block(ispi, op->data.buf.in, nbytes);
480 static int intel_spi_write_reg(struct intel_spi *ispi, const struct spi_mem *mem,
484 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;
501 if (!ispi->swseq_reg)
504 preop = readw(ispi->sregs + PREOP_OPTYPE);
506 if (ispi->locked)
508 writel(opcode, ispi->sregs + PREOP_OPTYPE);
515 ispi->atomic_preopcode = opcode;
528 writel(addr, ispi->base + FADDR);
531 ret = intel_spi_write_block(ispi, op->data.buf.out, nbytes);
535 if (ispi->swseq_reg)
536 return intel_spi_sw_cycle(ispi, opcode, nbytes,
538 return intel_spi_hw_cycle(ispi, iop, nbytes);
541 static int intel_spi_read(struct intel_spi *ispi, const struct spi_mem *mem,
545 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;
555 if (WARN_ON_ONCE(ispi->atomic_preopcode))
556 ispi->atomic_preopcode = 0;
565 writel(addr, ispi->base + FADDR);
567 val = readl(ispi->base + HSFSTS_CTL);
573 writel(val, ispi->base + HSFSTS_CTL);
575 ret = intel_spi_wait_hw_busy(ispi);
579 status = readl(ispi->base + HSFSTS_CTL);
586 dev_err(ispi->dev, "read error: %x: %#x\n", addr, status);
590 ret = intel_spi_read_block(ispi, read_buf, block_size);
602 static int intel_spi_write(struct intel_spi *ispi, const struct spi_mem *mem,
606 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;
613 ispi->atomic_preopcode = 0;
622 writel(addr, ispi->base + FADDR);
624 val = readl(ispi->base + HSFSTS_CTL);
630 ret = intel_spi_write_block(ispi, write_buf, block_size);
632 dev_err(ispi->dev, "failed to write block\n");
638 writel(val, ispi->base + HSFSTS_CTL);
640 ret = intel_spi_wait_hw_busy(ispi);
642 dev_err(ispi->dev, "timeout\n");
646 status = readl(ispi->base + HSFSTS_CTL);
653 dev_err(ispi->dev, "write error: %x: %#x\n", addr, status);
665 static int intel_spi_erase(struct intel_spi *ispi, const struct spi_mem *mem,
669 u32 addr = intel_spi_chip_addr(ispi, mem) + op->addr.val;
674 writel(addr, ispi->base + FADDR);
676 if (ispi->swseq_erase)
677 return intel_spi_sw_cycle(ispi, opcode, 0,
681 ispi->atomic_preopcode = 0;
683 val = readl(ispi->base + HSFSTS_CTL);
688 writel(val, ispi->base + HSFSTS_CTL);
690 ret = intel_spi_wait_hw_busy(ispi);
694 status = readl(ispi->base + HSFSTS_CTL);
735 intel_spi_match_mem_op(struct intel_spi *ispi, const struct spi_mem_op *op)
739 for (iop = ispi->mem_ops; iop->mem_op.cmd.opcode; iop++) {
750 struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller);
753 iop = intel_spi_match_mem_op(ispi, op);
755 dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);
763 if (ispi->swseq_reg && ispi->locked) {
767 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) {
768 if (ispi->opcodes[i] == op->cmd.opcode)
772 dev_dbg(ispi->dev, "%#x not supported\n", op->cmd.opcode);
781 struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller);
784 iop = intel_spi_match_mem_op(ispi, op);
788 return iop->exec_op(ispi, mem, iop, op);
793 const struct intel_spi *ispi = spi_controller_get_devdata(mem->spi->controller);
799 return dev_name(ispi->dev);
804 struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);
807 iop = intel_spi_match_mem_op(ispi, &desc->info.op_tmpl);
818 struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);
828 ret = iop->exec_op(ispi, desc->mem, iop, &op);
835 struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);
844 ret = iop->exec_op(ispi, desc->mem, iop, &op);
1069 static int intel_spi_init(struct intel_spi *ispi)
1075 switch (ispi->info->type) {
1077 ispi->sregs = ispi->base + BYT_SSFSTS_CTL;
1078 ispi->pregs = ispi->base + BYT_PR;
1079 ispi->nregions = BYT_FREG_NUM;
1080 ispi->pr_num = BYT_PR_NUM;
1081 ispi->swseq_reg = true;
1085 ispi->sregs = ispi->base + LPT_SSFSTS_CTL;
1086 ispi->pregs = ispi->base + LPT_PR;
1087 ispi->nregions = LPT_FREG_NUM;
1088 ispi->pr_num = LPT_PR_NUM;
1089 ispi->swseq_reg = true;
1093 ispi->sregs = ispi->base + BXT_SSFSTS_CTL;
1094 ispi->pregs = ispi->base + BXT_PR;
1095 ispi->nregions = BXT_FREG_NUM;
1096 ispi->pr_num = BXT_PR_NUM;
1101 ispi->sregs = NULL;
1102 ispi->pregs = ispi->base + CNL_PR;
1103 ispi->nregions = CNL_FREG_NUM;
1104 ispi->pr_num = CNL_PR_NUM;
1113 if (writeable && !intel_spi_set_writeable(ispi)) {
1114 dev_warn(ispi->dev, "can't disable chip write protection\n");
1119 val = readl(ispi->base + HSFSTS_CTL);
1121 writel(val, ispi->base + HSFSTS_CTL);
1131 lvscc = readl(ispi->base + LVSCC);
1132 uvscc = readl(ispi->base + UVSCC);
1134 ispi->swseq_erase = true;
1136 if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase)
1141 if (!ispi->sregs && (ispi->swseq_reg || ispi->swseq_erase)) {
1142 dev_err(ispi->dev, "software sequencer not supported, but required\n");
1151 if (ispi->swseq_reg) {
1153 val = readl(ispi->sregs + SSFSTS_CTL);
1155 writel(val, ispi->sregs + SSFSTS_CTL);
1159 val = readl(ispi->base + HSFSTS_CTL);
1160 ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);
1162 if (ispi->locked && ispi->sregs) {
1168 opmenu0 = readl(ispi->sregs + OPMENU0);
1169 opmenu1 = readl(ispi->sregs + OPMENU1);
1172 for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {
1173 ispi->opcodes[i] = opmenu0 >> i * 8;
1174 ispi->opcodes[i + 4] = opmenu1 >> i * 8;
1180 dev_dbg(ispi->dev, "Using erase_64k memory operations");
1181 ispi->mem_ops = erase_64k_mem_ops;
1183 dev_dbg(ispi->dev, "Using generic memory operations");
1184 ispi->mem_ops = generic_mem_ops;
1187 intel_spi_dump_regs(ispi);
1191 static bool intel_spi_is_protected(const struct intel_spi *ispi,
1196 for (i = 0; i < ispi->pr_num; i++) {
1199 pr_value = readl(ispi->pregs + PR(i));
1217 static void intel_spi_fill_partition(struct intel_spi *ispi,
1233 for (i = 1; i < ispi->nregions; i++) {
1236 region = readl(ispi->base + FREG(i));
1250 if (!writeable || intel_spi_is_protected(ispi, base, limit))
1259 static int intel_spi_read_desc(struct intel_spi *ispi)
1273 ret = intel_spi_read(ispi, NULL, NULL, &op);
1275 dev_warn(ispi->dev, "failed to read descriptor\n");
1279 dev_dbg(ispi->dev, "FLVALSIG=0x%08x\n", buf[0]);
1280 dev_dbg(ispi->dev, "FLMAP0=0x%08x\n", buf[1]);
1283 dev_warn(ispi->dev, "descriptor signature not valid\n");
1288 dev_dbg(ispi->dev, "FCBA=%#x\n", fcba);
1294 ret = intel_spi_read(ispi, NULL, NULL, &op);
1296 dev_warn(ispi->dev, "failed to read FLCOMP\n");
1300 dev_dbg(ispi->dev, "FLCOMP=0x%08x\n", flcomp);
1304 ispi->chip0_size = SZ_512K;
1307 ispi->chip0_size = SZ_1M;
1310 ispi->chip0_size = SZ_2M;
1313 ispi->chip0_size = SZ_4M;
1316 ispi->chip0_size = SZ_8M;
1319 ispi->chip0_size = SZ_16M;
1322 ispi->chip0_size = SZ_32M;
1325 ispi->chip0_size = SZ_64M;
1331 dev_dbg(ispi->dev, "chip0 size %zd KB\n", ispi->chip0_size / SZ_1K);
1335 ispi->host->num_chipselect = 1;
1337 ispi->host->num_chipselect = 2;
1341 dev_dbg(ispi->dev, "%u flash components found\n",
1342 ispi->host->num_chipselect);
1346 static int intel_spi_populate_chip(struct intel_spi *ispi)
1352 pdata = devm_kzalloc(ispi->dev, sizeof(*pdata), GFP_KERNEL);
1357 pdata->parts = devm_kcalloc(ispi->dev, pdata->nr_parts,
1362 intel_spi_fill_partition(ispi, pdata->parts);
1368 if (!spi_new_device(ispi->host, &chip))
1371 ret = intel_spi_read_desc(ispi);
1376 if (ispi->host->num_chipselect < 2)
1382 if (!spi_new_device(ispi->host, &chip))
1400 struct intel_spi *ispi;
1403 host = devm_spi_alloc_host(dev, sizeof(*ispi));
1409 ispi = spi_controller_get_devdata(host);
1411 ispi->base = devm_ioremap_resource(dev, mem);
1412 if (IS_ERR(ispi->base))
1413 return PTR_ERR(ispi->base);
1415 ispi->dev = dev;
1416 ispi->host = host;
1417 ispi->info = info;
1419 ret = intel_spi_init(ispi);
1427 return intel_spi_populate_chip(ispi);