Lines Matching defs:ctrl
513 u32 ctrl;
515 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
516 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
517 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
532 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
541 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
543 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
549 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
552 ctrl |= MX51_ECSPI_CTRL_CS(channel);
555 * The ctrl register must be written first, with the EN bit set other
558 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
654 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
658 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
660 ctrl |= (spi_imx->target_burst * 8 - 1)
664 ctrl |= (spi_imx->bits_per_word - 1)
668 ctrl |= (MX51_ECSPI_CTRL_MAX_BURST * BITS_PER_BYTE - 1)
671 ctrl |= (spi_imx->count / DIV_ROUND_UP(spi_imx->bits_per_word,
678 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
680 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
690 ctrl |= MX51_ECSPI_CTRL_SMC;
692 ctrl &= ~MX51_ECSPI_CTRL_SMC;
694 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1131 u32 ctrl;
1133 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1134 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1135 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1136 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);