Lines Matching refs:se
16 #include <linux/soc/qcom/geni-se.h>
79 struct geni_se se;
108 struct geni_se *se = &mas->se;
110 writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN);
111 writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL);
112 writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START);
125 ret = geni_se_clk_freq_match(&mas->se,
153 struct geni_se *se = &mas->se;
158 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
173 geni_se_cancel_m_cmd(se);
182 geni_se_abort_m_cmd(se);
202 writel(1, se->base + SE_DMA_TX_FSM_RST);
211 writel(1, se->base + SE_DMA_RX_FSM_RST);
255 struct geni_se *se = &mas->se;
268 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
269 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN);
291 struct geni_se *se = &mas->se;
317 geni_se_select_mode(se, mas->cur_xfer_mode);
321 geni_se_setup_m_cmd(se, SPI_CS_ASSERT, 0);
323 geni_se_setup_m_cmd(se, SPI_CS_DEASSERT, 0);
341 struct geni_se *se = &mas->se;
352 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first,
355 writel(word_len, se->base + SE_SPI_WORD_LEN);
362 struct geni_se *se = &mas->se;
385 writel(clk_sel, se->base + SE_GENI_CLK_SEL);
386 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG);
389 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
390 ret = geni_icc_set_bw(se);
401 struct geni_se *se = &mas->se;
422 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK);
423 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL);
424 writel(cpha, se->base + SE_SPI_CPHA);
425 writel(cpol, se->base + SE_SPI_CPOL);
426 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV);
651 struct geni_se *se = &mas->se;
658 proto = geni_se_read_proto(se);
670 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se);
673 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se);
679 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2);
682 ver = geni_se_get_qup_hw_version(se);
691 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
697 geni_se_select_mode(se, GENI_GPI_DMA);
712 geni_se_select_mode(se, GENI_SE_FIFO);
719 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
721 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
745 struct geni_se *se = &mas->se;
753 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
771 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1);
775 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
783 struct geni_se *se = &mas->se;
791 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS);
803 readl(se->base + SE_GENI_RX_FIFOn);
818 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1);
831 struct geni_se *se = &mas->se;
868 writel(len, se->base + SE_SPI_TX_TRANS_LEN);
873 writel(len, se->base + SE_SPI_RX_TRANS_LEN);
891 geni_se_select_mode(se, mas->cur_xfer_mode);
898 geni_se_setup_m_cmd(se, m_cmd, FRAGMENTATION);
902 geni_se_rx_init_dma(se, sg_dma_address(xfer->rx_sg.sgl),
905 geni_se_tx_init_dma(se, sg_dma_address(xfer->tx_sg.sgl),
909 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG);
944 struct geni_se *se = &mas->se;
947 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS);
983 writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
996 u32 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT);
997 u32 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT);
1000 writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR);
1002 writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR);
1035 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR);
1063 clk = devm_clk_get(dev, "se");
1075 mas->se.dev = dev;
1076 mas->se.wrapper = dev_get_drvdata(dev->parent);
1077 mas->se.base = base;
1078 mas->se.clk = clk;
1080 ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1118 ret = geni_icc_get(&mas->se, NULL);
1122 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ);
1123 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1125 ret = geni_icc_set_bw(&mas->se);
1188 ret = geni_se_resources_off(&mas->se);
1192 return geni_icc_disable(&mas->se);
1201 ret = geni_icc_enable(&mas->se);
1205 ret = geni_se_resources_on(&mas->se);