Lines Matching refs:reg_base

93 	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
94 	__be32 __iomem *mode = &reg_base->mode;
238 	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
243 	mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
247 	mpc8xxx_spi_write_reg(&reg_base->transmit, word);
256 	struct fsl_spi_reg __iomem *reg_base;
261 	reg_base = mpc8xxx_spi->reg_base;
286 	mpc8xxx_spi_write_reg(&reg_base->mask, 0);
372 	struct fsl_spi_reg __iomem *reg_base;
390 	reg_base = mpc8xxx_spi->reg_base;
393 	cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
428 	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
432 		u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
441 			mpc8xxx_spi_read_reg(&reg_base->event)) &
446 	mpc8xxx_spi_write_reg(&reg_base->event, events);
452 		mpc8xxx_spi_write_reg(&reg_base->transmit, word);
463 	struct fsl_spi_reg __iomem *reg_base = mspi->reg_base;
466 	events = mpc8xxx_spi_read_reg(&reg_base->event);
483 	struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
488 		slvsel = mpc8xxx_spi_read_reg(&reg_base->slvsel);
490 		mpc8xxx_spi_write_reg(&reg_base->slvsel, slvsel);
498 	struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
502 	capabilities = mpc8xxx_spi_read_reg(&reg_base->cap);
512 		mpc8xxx_spi_write_reg(&reg_base->slvsel, 0xffffffff);
535 	struct fsl_spi_reg __iomem *reg_base;
565 	mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
566 	if (IS_ERR(mpc8xxx_spi->reg_base)) {
567 		ret = PTR_ERR(mpc8xxx_spi->reg_base);
599 	reg_base = mpc8xxx_spi->reg_base;
602 	mpc8xxx_spi_write_reg(&reg_base->mode, 0);
603 	mpc8xxx_spi_write_reg(&reg_base->mask, 0);
604 	mpc8xxx_spi_write_reg(&reg_base->command, 0);
605 	mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
616 	mpc8xxx_spi_write_reg(&reg_base->mode, regval);
622 	dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,