Lines Matching refs:mpc8xxx_spi
91 struct mpc8xxx_spi *mspi = spi_controller_get_devdata(spi->controller);
150 struct mpc8xxx_spi *mpc8xxx_spi,
166 if (mpc8xxx_spi->set_shifts)
167 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
171 mpc8xxx_spi->rx_shift = cs->rx_shift;
172 mpc8xxx_spi->tx_shift = cs->tx_shift;
173 mpc8xxx_spi->get_rx = cs->get_rx;
174 mpc8xxx_spi->get_tx = cs->get_tx;
180 struct mpc8xxx_spi *mpc8xxx_spi;
186 mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
200 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
201 mspi_apply_cpu_mode_quirks(cs, spi, mpc8xxx_spi, bits_per_word);
214 if ((mpc8xxx_spi->spibrg / hz) > 64) {
216 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
219 dev_name(&spi->dev), hz, mpc8xxx_spi->spibrg / 1024);
223 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
234 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
255 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
261 reg_base = mpc8xxx_spi->reg_base;
271 mpc8xxx_spi->tx = t->tx_buf;
272 mpc8xxx_spi->rx = t->rx_buf;
274 reinit_completion(&mpc8xxx_spi->done);
276 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
277 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
279 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
283 wait_for_completion(&mpc8xxx_spi->done);
288 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
289 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
291 return mpc8xxx_spi->count;
297 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(ctlr);
318 if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) {
339 (mpc8xxx_spi->flags & SPI_CPM1))
371 struct mpc8xxx_spi *mpc8xxx_spi;
388 mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
390 reg_base = mpc8xxx_spi->reg_base;
426 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
460 struct mpc8xxx_spi *mspi = context_data;
482 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(spi->controller);
483 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
487 if (cs < mpc8xxx_spi->native_chipselects) {
497 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host);
498 struct fsl_spi_reg __iomem *reg_base = mpc8xxx_spi->reg_base;
504 mpc8xxx_spi->set_shifts = fsl_spi_grlib_set_shifts;
507 mpc8xxx_spi->max_bits_per_word = mbits + 1;
509 mpc8xxx_spi->native_chipselects = 0;
511 mpc8xxx_spi->native_chipselects = SPCAP_SSSZ(capabilities);
514 host->num_chipselect = mpc8xxx_spi->native_chipselects;
534 struct mpc8xxx_spi *mpc8xxx_spi;
539 host = spi_alloc_host(dev, sizeof(struct mpc8xxx_spi));
557 mpc8xxx_spi = spi_controller_get_devdata(host);
558 mpc8xxx_spi->max_bits_per_word = 32;
559 mpc8xxx_spi->type = fsl_spi_get_type(dev);
561 ret = fsl_spi_cpm_init(mpc8xxx_spi);
565 mpc8xxx_spi->reg_base = devm_ioremap_resource(dev, mem);
566 if (IS_ERR(mpc8xxx_spi->reg_base)) {
567 ret = PTR_ERR(mpc8xxx_spi->reg_base);
571 if (mpc8xxx_spi->type == TYPE_GRLIB)
574 if (mpc8xxx_spi->flags & SPI_CPM_MODE)
582 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word);
584 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
585 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
587 if (mpc8xxx_spi->set_shifts)
589 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
590 &mpc8xxx_spi->tx_shift, 8, 1);
593 ret = devm_request_irq(dev, mpc8xxx_spi->irq, fsl_spi_irq,
594 0, "fsl_spi", mpc8xxx_spi);
599 reg_base = mpc8xxx_spi->reg_base;
609 if (mpc8xxx_spi->max_bits_per_word < 8) {
611 regval |= SPMODE_LEN(mpc8xxx_spi->max_bits_per_word - 1);
613 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
623 mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
628 fsl_spi_cpm_free(mpc8xxx_spi);
707 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host);
709 fsl_spi_cpm_free(mpc8xxx_spi);
753 struct mpc8xxx_spi *mpc8xxx_spi = spi_controller_get_devdata(host);
755 fsl_spi_cpm_free(mpc8xxx_spi);
758 MODULE_ALIAS("platform:mpc8xxx_spi");
763 .name = "mpc8xxx_spi",