Lines Matching refs:fsl_lpspi
29 #define DRIVER_NAME "fsl_lpspi"
131 static void fsl_lpspi_buf_rx_##type(struct fsl_lpspi_data *fsl_lpspi) \
133 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
135 if (fsl_lpspi->rx_buf) { \
136 *(type *)fsl_lpspi->rx_buf = val; \
137 fsl_lpspi->rx_buf += sizeof(type); \
142 static void fsl_lpspi_buf_tx_##type(struct fsl_lpspi_data *fsl_lpspi) \
146 if (fsl_lpspi->tx_buf) { \
147 val = *(type *)fsl_lpspi->tx_buf; \
148 fsl_lpspi->tx_buf += sizeof(type); \
151 fsl_lpspi->remain -= sizeof(type); \
152 writel(val, fsl_lpspi->base + IMX7ULP_TDR); \
162 static void fsl_lpspi_intctrl(struct fsl_lpspi_data *fsl_lpspi,
165 writel(enable, fsl_lpspi->base + IMX7ULP_IER);
198 struct fsl_lpspi_data *fsl_lpspi =
202 ret = pm_runtime_resume_and_get(fsl_lpspi->dev);
204 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
213 struct fsl_lpspi_data *fsl_lpspi =
216 pm_runtime_mark_last_busy(fsl_lpspi->dev);
217 pm_runtime_put_autosuspend(fsl_lpspi->dev);
222 static void fsl_lpspi_write_tx_fifo(struct fsl_lpspi_data *fsl_lpspi)
227 txfifo_cnt = readl(fsl_lpspi->base + IMX7ULP_FSR) & 0xff;
229 while (txfifo_cnt < fsl_lpspi->txfifosize) {
230 if (!fsl_lpspi->remain)
232 fsl_lpspi->tx(fsl_lpspi);
236 if (txfifo_cnt < fsl_lpspi->txfifosize) {
237 if (!fsl_lpspi->is_target) {
238 temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
240 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
243 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
245 fsl_lpspi_intctrl(fsl_lpspi, IER_TDIE);
248 static void fsl_lpspi_read_rx_fifo(struct fsl_lpspi_data *fsl_lpspi)
250 while (!(readl(fsl_lpspi->base + IMX7ULP_RSR) & RSR_RXEMPTY))
251 fsl_lpspi->rx(fsl_lpspi);
254 static void fsl_lpspi_set_cmd(struct fsl_lpspi_data *fsl_lpspi)
258 temp |= fsl_lpspi->config.bpw - 1;
259 temp |= (fsl_lpspi->config.mode & 0x3) << 30;
260 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
261 if (!fsl_lpspi->is_target) {
262 temp |= fsl_lpspi->config.prescale << 27;
268 if (!fsl_lpspi->usedma) {
270 if (fsl_lpspi->is_first_byte)
276 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
278 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
281 static void fsl_lpspi_set_watermark(struct fsl_lpspi_data *fsl_lpspi)
285 if (!fsl_lpspi->usedma)
286 temp = fsl_lpspi->watermark >> 1 |
287 (fsl_lpspi->watermark >> 1) << 16;
289 temp = fsl_lpspi->watermark >> 1;
291 writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
293 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
296 static int fsl_lpspi_set_bitrate(struct fsl_lpspi_data *fsl_lpspi)
298 struct lpspi_config config = fsl_lpspi->config;
302 perclk_rate = clk_get_rate(fsl_lpspi->clk_per);
305 dev_err(fsl_lpspi->dev,
311 dev_err(fsl_lpspi->dev,
319 fsl_lpspi->config.prescale = prescale;
328 fsl_lpspi->base + IMX7ULP_CCR);
330 dev_dbg(fsl_lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n",
341 struct fsl_lpspi_data *fsl_lpspi =
344 switch (fsl_lpspi_bytes_per_word(fsl_lpspi->config.bpw)) {
359 tx.dst_addr = fsl_lpspi->base_phys + IMX7ULP_TDR;
364 dev_err(fsl_lpspi->dev, "TX dma configuration failed with %d\n",
370 rx.src_addr = fsl_lpspi->base_phys + IMX7ULP_RDR;
375 dev_err(fsl_lpspi->dev, "RX dma configuration failed with %d\n",
383 static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
388 if (!fsl_lpspi->is_target) {
389 ret = fsl_lpspi_set_bitrate(fsl_lpspi);
394 fsl_lpspi_set_watermark(fsl_lpspi);
396 if (!fsl_lpspi->is_target)
400 if (fsl_lpspi->config.mode & SPI_CS_HIGH)
402 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
404 temp = readl(fsl_lpspi->base + IMX7ULP_CR);
406 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
409 if (fsl_lpspi->usedma)
411 writel(temp, fsl_lpspi->base + IMX7ULP_DER);
420 struct fsl_lpspi_data *fsl_lpspi =
426 fsl_lpspi->config.mode = spi->mode;
427 fsl_lpspi->config.bpw = t->bits_per_word;
428 fsl_lpspi->config.speed_hz = t->speed_hz;
429 if (fsl_lpspi->is_only_cs1)
430 fsl_lpspi->config.chip_select = 1;
432 fsl_lpspi->config.chip_select = spi_get_chipselect(spi, 0);
434 if (!fsl_lpspi->config.speed_hz)
435 fsl_lpspi->config.speed_hz = spi->max_speed_hz;
436 if (!fsl_lpspi->config.bpw)
437 fsl_lpspi->config.bpw = spi->bits_per_word;
440 if (fsl_lpspi->config.bpw <= 8) {
441 fsl_lpspi->rx = fsl_lpspi_buf_rx_u8;
442 fsl_lpspi->tx = fsl_lpspi_buf_tx_u8;
443 } else if (fsl_lpspi->config.bpw <= 16) {
444 fsl_lpspi->rx = fsl_lpspi_buf_rx_u16;
445 fsl_lpspi->tx = fsl_lpspi_buf_tx_u16;
447 fsl_lpspi->rx = fsl_lpspi_buf_rx_u32;
448 fsl_lpspi->tx = fsl_lpspi_buf_tx_u32;
451 if (t->len <= fsl_lpspi->txfifosize)
452 fsl_lpspi->watermark = t->len;
454 fsl_lpspi->watermark = fsl_lpspi->txfifosize;
457 fsl_lpspi->usedma = true;
459 fsl_lpspi->usedma = false;
461 return fsl_lpspi_config(fsl_lpspi);
466 struct fsl_lpspi_data *fsl_lpspi =
469 fsl_lpspi->target_aborted = true;
470 if (!fsl_lpspi->usedma)
471 complete(&fsl_lpspi->xfer_done);
473 complete(&fsl_lpspi->dma_tx_completion);
474 complete(&fsl_lpspi->dma_rx_completion);
482 struct fsl_lpspi_data *fsl_lpspi =
485 if (fsl_lpspi->is_target) {
486 if (wait_for_completion_interruptible(&fsl_lpspi->xfer_done) ||
487 fsl_lpspi->target_aborted) {
488 dev_dbg(fsl_lpspi->dev, "interrupted\n");
492 if (!wait_for_completion_timeout(&fsl_lpspi->xfer_done, HZ)) {
493 dev_dbg(fsl_lpspi->dev, "wait for completion timeout\n");
501 static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
505 if (!fsl_lpspi->usedma) {
507 fsl_lpspi_intctrl(fsl_lpspi, 0);
512 writel(temp, fsl_lpspi->base + IMX7ULP_SR);
516 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
523 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
525 complete(&fsl_lpspi->dma_rx_completion);
530 struct fsl_lpspi_data *fsl_lpspi = (struct fsl_lpspi_data *)cookie;
532 complete(&fsl_lpspi->dma_tx_completion);
535 static int fsl_lpspi_calculate_timeout(struct fsl_lpspi_data *fsl_lpspi,
541 timeout = (8 + 4) * size / fsl_lpspi->config.speed_hz;
551 struct fsl_lpspi_data *fsl_lpspi,
571 desc_rx->callback_param = (void *)fsl_lpspi;
573 reinit_completion(&fsl_lpspi->dma_rx_completion);
585 desc_tx->callback_param = (void *)fsl_lpspi;
587 reinit_completion(&fsl_lpspi->dma_tx_completion);
590 fsl_lpspi->target_aborted = false;
592 if (!fsl_lpspi->is_target) {
593 transfer_timeout = fsl_lpspi_calculate_timeout(fsl_lpspi,
597 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_tx_completion,
600 dev_err(fsl_lpspi->dev, "I/O Error in DMA TX\n");
603 fsl_lpspi_reset(fsl_lpspi);
607 timeout = wait_for_completion_timeout(&fsl_lpspi->dma_rx_completion,
610 dev_err(fsl_lpspi->dev, "I/O Error in DMA RX\n");
613 fsl_lpspi_reset(fsl_lpspi);
617 if (wait_for_completion_interruptible(&fsl_lpspi->dma_tx_completion) ||
618 fsl_lpspi->target_aborted) {
619 dev_dbg(fsl_lpspi->dev,
623 fsl_lpspi_reset(fsl_lpspi);
627 if (wait_for_completion_interruptible(&fsl_lpspi->dma_rx_completion) ||
628 fsl_lpspi->target_aborted) {
629 dev_dbg(fsl_lpspi->dev,
633 fsl_lpspi_reset(fsl_lpspi);
638 fsl_lpspi_reset(fsl_lpspi);
657 struct fsl_lpspi_data *fsl_lpspi,
680 init_completion(&fsl_lpspi->dma_rx_completion);
681 init_completion(&fsl_lpspi->dma_tx_completion);
694 struct fsl_lpspi_data *fsl_lpspi =
698 fsl_lpspi->tx_buf = t->tx_buf;
699 fsl_lpspi->rx_buf = t->rx_buf;
700 fsl_lpspi->remain = t->len;
702 reinit_completion(&fsl_lpspi->xfer_done);
703 fsl_lpspi->target_aborted = false;
705 fsl_lpspi_write_tx_fifo(fsl_lpspi);
711 fsl_lpspi_reset(fsl_lpspi);
720 struct fsl_lpspi_data *fsl_lpspi =
724 fsl_lpspi->is_first_byte = true;
729 fsl_lpspi_set_cmd(fsl_lpspi);
730 fsl_lpspi->is_first_byte = false;
732 if (fsl_lpspi->usedma)
733 ret = fsl_lpspi_dma_transfer(controller, fsl_lpspi, t);
745 struct fsl_lpspi_data *fsl_lpspi = dev_id;
747 temp_IER = readl(fsl_lpspi->base + IMX7ULP_IER);
748 fsl_lpspi_intctrl(fsl_lpspi, 0);
749 temp_SR = readl(fsl_lpspi->base + IMX7ULP_SR);
751 fsl_lpspi_read_rx_fifo(fsl_lpspi);
754 fsl_lpspi_write_tx_fifo(fsl_lpspi);
759 readl(fsl_lpspi->base + IMX7ULP_FSR) & FSR_TXCOUNT) {
760 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
761 fsl_lpspi_intctrl(fsl_lpspi, IER_FCIE);
766 writel(SR_FCF, fsl_lpspi->base + IMX7ULP_SR);
767 complete(&fsl_lpspi->xfer_done);
778 struct fsl_lpspi_data *fsl_lpspi;
781 fsl_lpspi = spi_controller_get_devdata(controller);
783 ret = clk_prepare_enable(fsl_lpspi->clk_per);
787 ret = clk_prepare_enable(fsl_lpspi->clk_ipg);
789 clk_disable_unprepare(fsl_lpspi->clk_per);
799 struct fsl_lpspi_data *fsl_lpspi;
801 fsl_lpspi = spi_controller_get_devdata(controller);
803 clk_disable_unprepare(fsl_lpspi->clk_per);
804 clk_disable_unprepare(fsl_lpspi->clk_ipg);
810 static int fsl_lpspi_init_rpm(struct fsl_lpspi_data *fsl_lpspi)
812 struct device *dev = fsl_lpspi->dev;
823 struct fsl_lpspi_data *fsl_lpspi;
844 fsl_lpspi = spi_controller_get_devdata(controller);
845 fsl_lpspi->dev = &pdev->dev;
846 fsl_lpspi->is_target = is_target;
847 fsl_lpspi->is_only_cs1 = of_property_read_bool((&pdev->dev)->of_node,
850 init_completion(&fsl_lpspi->xfer_done);
852 fsl_lpspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
853 if (IS_ERR(fsl_lpspi->base)) {
854 ret = PTR_ERR(fsl_lpspi->base);
857 fsl_lpspi->base_phys = res->start;
866 dev_name(&pdev->dev), fsl_lpspi);
872 fsl_lpspi->clk_per = devm_clk_get(&pdev->dev, "per");
873 if (IS_ERR(fsl_lpspi->clk_per)) {
874 ret = PTR_ERR(fsl_lpspi->clk_per);
878 fsl_lpspi->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
879 if (IS_ERR(fsl_lpspi->clk_ipg)) {
880 ret = PTR_ERR(fsl_lpspi->clk_ipg);
885 ret = fsl_lpspi_init_rpm(fsl_lpspi);
889 ret = pm_runtime_get_sync(fsl_lpspi->dev);
891 dev_err(fsl_lpspi->dev, "failed to enable clock\n");
895 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
896 fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
897 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
916 if (!fsl_lpspi->is_target)
919 ret = fsl_lpspi_dma_init(&pdev->dev, fsl_lpspi, controller);
937 pm_runtime_mark_last_busy(fsl_lpspi->dev);
938 pm_runtime_put_autosuspend(fsl_lpspi->dev);
945 pm_runtime_dont_use_autosuspend(fsl_lpspi->dev);
946 pm_runtime_put_sync(fsl_lpspi->dev);
947 pm_runtime_disable(fsl_lpspi->dev);
957 struct fsl_lpspi_data *fsl_lpspi =
962 pm_runtime_disable(fsl_lpspi->dev);