Lines Matching defs:temp
225 u32 temp;
238 temp = readl(fsl_lpspi->base + IMX7ULP_TCR);
239 temp &= ~TCR_CONTC;
240 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
256 u32 temp = 0;
258 temp |= fsl_lpspi->config.bpw - 1;
259 temp |= (fsl_lpspi->config.mode & 0x3) << 30;
260 temp |= (fsl_lpspi->config.chip_select & 0x3) << 24;
262 temp |= fsl_lpspi->config.prescale << 27;
269 temp |= TCR_CONT;
271 temp &= ~TCR_CONTC;
273 temp |= TCR_CONTC;
276 writel(temp, fsl_lpspi->base + IMX7ULP_TCR);
278 dev_dbg(fsl_lpspi->dev, "TCR=0x%x\n", temp);
283 u32 temp;
286 temp = fsl_lpspi->watermark >> 1 |
289 temp = fsl_lpspi->watermark >> 1;
291 writel(temp, fsl_lpspi->base + IMX7ULP_FCR);
293 dev_dbg(fsl_lpspi->dev, "FCR=0x%x\n", temp);
385 u32 temp;
397 temp = CFGR1_HOST;
399 temp = CFGR1_PINCFG;
401 temp |= CFGR1_PCSPOL;
402 writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
404 temp = readl(fsl_lpspi->base + IMX7ULP_CR);
405 temp |= CR_RRF | CR_RTF | CR_MEN;
406 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
408 temp = 0;
410 temp = DER_TDDE | DER_RDDE;
411 writel(temp, fsl_lpspi->base + IMX7ULP_DER);
503 u32 temp;
511 temp = 0x3F << 8;
512 writel(temp, fsl_lpspi->base + IMX7ULP_SR);
515 temp = CR_RRF | CR_RTF;
516 writel(temp, fsl_lpspi->base + IMX7ULP_CR);
828 u32 temp;
895 temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
896 fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
897 fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
901 num_cs = ((temp >> 16) & 0xf);