Lines Matching refs:dln2
12 #include <linux/mfd/dln2.h>
102 static int dln2_spi_enable(struct dln2_spi *dln2, bool enable)
111 tx.port = dln2->port;
121 return dln2_transfer_tx(dln2->pdev, cmd, &tx, len);
132 static int dln2_spi_cs_set(struct dln2_spi *dln2, u8 cs_mask)
139 tx.port = dln2->port;
148 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_SS, &tx, sizeof(tx));
154 static int dln2_spi_cs_set_one(struct dln2_spi *dln2, u8 cs)
156 return dln2_spi_cs_set(dln2, BIT(cs));
162 static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable)
170 tx.port = dln2->port;
174 return dln2_transfer_tx(dln2->pdev, cmd, &tx, sizeof(tx));
177 static int dln2_spi_cs_enable_all(struct dln2_spi *dln2, bool enable)
179 u8 cs_mask = GENMASK(dln2->host->num_chipselect - 1, 0);
181 return dln2_spi_cs_enable(dln2, cs_mask, enable);
184 static int dln2_spi_get_cs_num(struct dln2_spi *dln2, u16 *cs_num)
195 tx.port = dln2->port;
196 ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SS_COUNT, &tx, sizeof(tx),
205 dev_dbg(&dln2->pdev->dev, "cs_num = %d\n", *cs_num);
210 static int dln2_spi_get_speed(struct dln2_spi *dln2, u16 cmd, u32 *freq)
221 tx.port = dln2->port;
223 ret = dln2_transfer(dln2->pdev, cmd, &tx, sizeof(tx), &rx, &rx_len);
237 static int dln2_spi_get_speed_range(struct dln2_spi *dln2, u32 *fmin, u32 *fmax)
241 ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MIN_FREQUENCY, fmin);
245 ret = dln2_spi_get_speed(dln2, DLN2_SPI_GET_MAX_FREQUENCY, fmax);
249 dev_dbg(&dln2->pdev->dev, "freq_min = %d, freq_max = %d\n",
259 static int dln2_spi_set_speed(struct dln2_spi *dln2, u32 speed)
271 tx.port = dln2->port;
274 ret = dln2_transfer(dln2->pdev, DLN2_SPI_SET_FREQUENCY, &tx, sizeof(tx),
287 static int dln2_spi_set_mode(struct dln2_spi *dln2, u8 mode)
294 tx.port = dln2->port;
297 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_MODE, &tx, sizeof(tx));
303 static int dln2_spi_set_bpw(struct dln2_spi *dln2, u8 bpw)
310 tx.port = dln2->port;
313 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_SET_FRAME_SIZE,
317 static int dln2_spi_get_supported_frame_sizes(struct dln2_spi *dln2,
327 } *rx = dln2->buf;
331 tx.port = dln2->port;
333 ret = dln2_transfer(dln2->pdev, DLN2_SPI_GET_SUPPORTED_FRAME_SIZES,
346 dev_dbg(&dln2->pdev->dev, "bpw_mask = 0x%X\n", *bpw_mask);
419 static int dln2_spi_write_one(struct dln2_spi *dln2, const u8 *data,
427 } __packed *tx = dln2->buf;
435 tx->port = dln2->port;
439 dln2_spi_copy_to_buf(tx->buf, data, data_len, dln2->bpw);
442 return dln2_transfer_tx(dln2->pdev, DLN2_SPI_WRITE, tx, tx_len);
448 static int dln2_spi_read_one(struct dln2_spi *dln2, u8 *data,
460 } __packed *rx = dln2->buf;
468 tx.port = dln2->port;
472 ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ, &tx, sizeof(tx),
481 dln2_spi_copy_from_buf(data, rx->buf, data_len, dln2->bpw);
489 static int dln2_spi_read_write_one(struct dln2_spi *dln2, const u8 *tx_data,
516 tx = dln2->buf;
517 rx = dln2->buf;
519 tx->port = dln2->port;
523 dln2_spi_copy_to_buf(tx->buf, tx_data, data_len, dln2->bpw);
528 ret = dln2_transfer(dln2->pdev, DLN2_SPI_READ_WRITE, tx, tx_len,
537 dln2_spi_copy_from_buf(rx_data, rx->buf, data_len, dln2->bpw);
546 static int dln2_spi_rdwr(struct dln2_spi *dln2, const u8 *tx_data,
567 ret = dln2_spi_read_write_one(dln2,
572 ret = dln2_spi_write_one(dln2,
576 ret = dln2_spi_read_one(dln2,
596 struct dln2_spi *dln2 = spi_controller_get_devdata(host);
599 if (dln2->cs != spi_get_chipselect(spi, 0)) {
600 ret = dln2_spi_cs_set_one(dln2, spi_get_chipselect(spi, 0));
604 dln2->cs = spi_get_chipselect(spi, 0);
610 static int dln2_spi_transfer_setup(struct dln2_spi *dln2, u32 speed,
616 bus_setup_change = dln2->speed != speed || dln2->mode != mode ||
617 dln2->bpw != bpw;
622 ret = dln2_spi_enable(dln2, false);
626 if (dln2->speed != speed) {
627 ret = dln2_spi_set_speed(dln2, speed);
631 dln2->speed = speed;
634 if (dln2->mode != mode) {
635 ret = dln2_spi_set_mode(dln2, mode & 0x3);
639 dln2->mode = mode;
642 if (dln2->bpw != bpw) {
643 ret = dln2_spi_set_bpw(dln2, bpw);
647 dln2->bpw = bpw;
650 return dln2_spi_enable(dln2, true);
657 struct dln2_spi *dln2 = spi_controller_get_devdata(host);
661 status = dln2_spi_transfer_setup(dln2, xfer->speed_hz,
665 dev_err(&dln2->pdev->dev, "Cannot setup transfer\n");
672 status = dln2_spi_rdwr(dln2, xfer->tx_buf, xfer->rx_buf,
675 dev_err(&dln2->pdev->dev, "write/read failed!\n");
683 struct dln2_spi *dln2;
688 host = spi_alloc_host(&pdev->dev, sizeof(*dln2));
696 dln2 = spi_controller_get_devdata(host);
698 dln2->buf = devm_kmalloc(&pdev->dev, DLN2_SPI_BUF_SIZE, GFP_KERNEL);
699 if (!dln2->buf) {
704 dln2->host = host;
705 dln2->pdev = pdev;
706 dln2->port = pdata->port;
708 dln2->cs = 0xff;
709 dln2->mode = 0xff;
712 ret = dln2_spi_enable(dln2, false);
718 ret = dln2_spi_get_cs_num(dln2, &host->num_chipselect);
724 ret = dln2_spi_get_speed_range(dln2,
732 ret = dln2_spi_get_supported_frame_sizes(dln2,
739 ret = dln2_spi_cs_enable_all(dln2, true);
752 ret = dln2_spi_enable(dln2, true);
776 if (dln2_spi_enable(dln2, false) < 0)
787 struct dln2_spi *dln2 = spi_controller_get_devdata(host);
791 if (dln2_spi_enable(dln2, false) < 0)
800 struct dln2_spi *dln2 = spi_controller_get_devdata(host);
807 ret = dln2_spi_enable(dln2, false);
816 dln2->cs = 0xff;
817 dln2->speed = 0;
818 dln2->bpw = 0;
819 dln2->mode = 0xff;
828 struct dln2_spi *dln2 = spi_controller_get_devdata(host);
831 ret = dln2_spi_cs_enable_all(dln2, true);
835 ret = dln2_spi_enable(dln2, true);
848 struct dln2_spi *dln2 = spi_controller_get_devdata(host);
850 return dln2_spi_enable(dln2, false);
856 struct dln2_spi *dln2 = spi_controller_get_devdata(host);
858 return dln2_spi_enable(dln2, true);
870 .name = "dln2-spi",
881 MODULE_ALIAS("platform:dln2-spi");