Lines Matching defs:dspi
134 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
136 if (dspi->rx) {
137 u8 *rx = dspi->rx;
139 dspi->rx = rx;
143 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
145 if (dspi->rx) {
146 u16 *rx = dspi->rx;
148 dspi->rx = rx;
152 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
156 if (dspi->tx) {
157 const u8 *tx = dspi->tx;
160 dspi->tx = tx;
165 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
169 if (dspi->tx) {
170 const u16 *tx = dspi->tx;
173 dspi->tx = tx;
199 struct davinci_spi *dspi;
204 dspi = spi_controller_get_devdata(spi->controller);
227 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
232 * @dspi: the controller data
241 static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
247 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz) - 1;
249 if (ret < dspi->prescaler_limit || ret > 255)
268 struct davinci_spi *dspi;
274 dspi = spi_controller_get_devdata(spi->controller);
293 dspi->get_rx = davinci_spi_rx_buf_u8;
294 dspi->get_tx = davinci_spi_tx_buf_u8;
295 dspi->bytes_per_word[spi_get_chipselect(spi, 0)] = 1;
297 dspi->get_rx = davinci_spi_rx_buf_u16;
298 dspi->get_tx = davinci_spi_tx_buf_u16;
299 dspi->bytes_per_word[spi_get_chipselect(spi, 0)] = 2;
307 prescale = davinci_spi_get_prescale(dspi, hz);
343 if (dspi->version == SPI_VERSION_2) {
370 iowrite32(delay, dspi->base + SPIDELAY);
373 iowrite32(spifmt, dspi->base + SPIFMT0);
382 struct davinci_spi *dspi = spi_controller_get_devdata(spi->controller);
395 if (dspi->dma_rx && dspi->dma_tx)
410 struct davinci_spi *dspi;
414 dspi = spi_controller_get_devdata(spi->controller);
421 set_io_bits(dspi->base + SPIPC0, 1 << spi_get_chipselect(spi, 0));
425 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
428 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
430 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
460 static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
462 struct device *sdev = dspi->bitbang.master->dev.parent;
477 if (dspi->version == SPI_VERSION_2) {
501 * @dspi: the controller data
506 static int davinci_spi_process_events(struct davinci_spi *dspi)
510 buf = ioread32(dspi->base + SPIBUF);
512 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
513 dspi->get_rx(buf & 0xFFFF, dspi);
514 dspi->rcount--;
517 status = ioread32(dspi->base + SPIFLG);
524 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
525 spidat1 = ioread32(dspi->base + SPIDAT1);
526 dspi->wcount--;
528 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
529 iowrite32(spidat1, dspi->base + SPIDAT1);
538 struct davinci_spi *dspi = (struct davinci_spi *)data;
540 dspi->rcount = 0;
542 if (!dspi->wcount && !dspi->rcount)
543 complete(&dspi->done);
548 struct davinci_spi *dspi = (struct davinci_spi *)data;
550 dspi->wcount = 0;
552 if (!dspi->wcount && !dspi->rcount)
553 complete(&dspi->done);
567 struct davinci_spi *dspi;
574 dspi = spi_controller_get_devdata(spi->controller);
575 pdata = &dspi->pdata;
581 data_type = dspi->bytes_per_word[spi_get_chipselect(spi, 0)];
583 dspi->tx = t->tx_buf;
584 dspi->rx = t->rx_buf;
585 dspi->wcount = t->len / data_type;
586 dspi->rcount = dspi->wcount;
588 spidat1 = ioread32(dspi->base + SPIDAT1);
590 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
591 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
593 reinit_completion(&dspi->done);
597 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
599 dspi->wcount--;
600 tx_data = dspi->get_tx(dspi);
603 iowrite32(spidat1, dspi->base + SPIDAT1);
607 .src_addr = (unsigned long)dspi->pbase + SPIBUF,
613 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
620 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
621 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
623 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
639 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
646 rxdesc->callback_param = (void *)dspi;
648 txdesc->callback_param = (void *)dspi;
651 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
656 dma_async_issue_pending(dspi->dma_rx);
657 dma_async_issue_pending(dspi->dma_tx);
659 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
664 if (wait_for_completion_timeout(&dspi->done, HZ) == 0)
667 while (dspi->rcount > 0 || dspi->wcount > 0) {
668 errors = davinci_spi_process_events(dspi);
675 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
677 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
679 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
680 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
687 ret = davinci_spi_check_error(dspi, errors);
693 if (dspi->rcount != 0 || dspi->wcount != 0) {
730 struct davinci_spi *dspi = data;
733 status = davinci_spi_process_events(dspi);
735 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
737 if ((!dspi->rcount && !dspi->wcount) || status)
738 complete(&dspi->done);
743 static int davinci_spi_request_dma(struct davinci_spi *dspi)
745 struct device *sdev = dspi->bitbang.master->dev.parent;
747 dspi->dma_rx = dma_request_chan(sdev, "rx");
748 if (IS_ERR(dspi->dma_rx))
749 return PTR_ERR(dspi->dma_rx);
751 dspi->dma_tx = dma_request_chan(sdev, "tx");
752 if (IS_ERR(dspi->dma_tx)) {
753 dma_release_channel(dspi->dma_rx);
754 return PTR_ERR(dspi->dma_tx);
803 * @dspi: ptr to driver data
805 * Parses and populates pdata in dspi from device tree bindings.
810 struct davinci_spi *dspi)
817 pdata = &dspi->pdata;
839 struct davinci_spi *dspi)
859 struct davinci_spi *dspi;
873 dspi = spi_controller_get_devdata(host);
877 dspi->pdata = *pdata;
879 /* update dspi pdata with that from the DT */
880 ret = spi_davinci_get_pdata(pdev, dspi);
885 /* pdata in dspi is now updated and point pdata to that */
886 pdata = &dspi->pdata;
888 dspi->bytes_per_word = devm_kcalloc(&pdev->dev,
890 sizeof(*dspi->bytes_per_word),
892 if (dspi->bytes_per_word == NULL) {
897 dspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
898 if (IS_ERR(dspi->base)) {
899 ret = PTR_ERR(dspi->base);
902 dspi->pbase = r->start;
904 init_completion(&dspi->done);
909 dspi->irq = ret;
911 ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
912 dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
916 dspi->bitbang.master = host;
918 dspi->clk = devm_clk_get(&pdev->dev, NULL);
919 if (IS_ERR(dspi->clk)) {
923 ret = clk_prepare_enable(dspi->clk);
937 dspi->bitbang.chipselect = davinci_spi_chipselect;
938 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
939 dspi->prescaler_limit = pdata->prescaler_limit;
940 dspi->version = pdata->version;
942 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP | SPI_CS_WORD;
943 if (dspi->version == SPI_VERSION_2)
944 dspi->bitbang.flags |= SPI_READY;
946 dspi->bitbang.txrx_bufs = davinci_spi_bufs;
948 ret = davinci_spi_request_dma(dspi);
953 dspi->dma_rx = NULL;
954 dspi->dma_tx = NULL;
957 dspi->get_rx = davinci_spi_rx_buf_u8;
958 dspi->get_tx = davinci_spi_tx_buf_u8;
961 iowrite32(0, dspi->base + SPIGCR0);
963 iowrite32(1, dspi->base + SPIGCR0);
967 iowrite32(spipc0, dspi->base + SPIPC0);
970 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
972 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
974 iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
977 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
978 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
979 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
981 ret = spi_bitbang_start(&dspi->bitbang);
985 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
990 if (dspi->dma_rx) {
991 dma_release_channel(dspi->dma_rx);
992 dma_release_channel(dspi->dma_tx);
995 clk_disable_unprepare(dspi->clk);
1013 struct davinci_spi *dspi;
1017 dspi = spi_controller_get_devdata(host);
1019 spi_bitbang_stop(&dspi->bitbang);
1021 clk_disable_unprepare(dspi->clk);
1023 if (dspi->dma_rx) {
1024 dma_release_channel(dspi->dma_rx);
1025 dma_release_channel(dspi->dma_tx);