Lines Matching defs:ctlr
33 struct spi_controller *ctlr;
113 static int cs42l43_transfer_one(struct spi_controller *ctlr, struct spi_device *spi,
155 static int cs42l43_prepare_message(struct spi_controller *ctlr, struct spi_message *msg)
157 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
176 static int cs42l43_prepare_transfer_hardware(struct spi_controller *ctlr)
178 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
188 static int cs42l43_unprepare_transfer_hardware(struct spi_controller *ctlr)
190 struct cs42l43_spi *priv = spi_controller_get_devdata(ctlr);
216 priv->ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*priv->ctlr));
217 if (!priv->ctlr)
220 spi_controller_set_devdata(priv->ctlr, priv);
225 priv->ctlr->prepare_message = cs42l43_prepare_message;
226 priv->ctlr->prepare_transfer_hardware = cs42l43_prepare_transfer_hardware;
227 priv->ctlr->unprepare_transfer_hardware = cs42l43_unprepare_transfer_hardware;
228 priv->ctlr->transfer_one = cs42l43_transfer_one;
229 priv->ctlr->set_cs = cs42l43_set_cs;
230 priv->ctlr->max_transfer_size = cs42l43_spi_max_length;
235 device_set_node(&priv->ctlr->dev, fwnode);
237 priv->ctlr->mode_bits = SPI_3WIRE | SPI_MODE_X_MASK;
238 priv->ctlr->flags = SPI_CONTROLLER_HALF_DUPLEX;
239 priv->ctlr->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
241 priv->ctlr->min_speed_hz = CS42L43_SPI_ROOT_HZ /
243 priv->ctlr->max_speed_hz = CS42L43_SPI_ROOT_HZ / cs42l43_clock_divs[0];
244 priv->ctlr->use_gpio_descriptors = true;
245 priv->ctlr->auto_runtime_pm = true;
260 ret = devm_spi_register_controller(priv->dev, priv->ctlr);