Lines Matching refs:ret
423 int ret;
432 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
434 if (ret) {
437 return ret;
473 int ret;
486 ret = cqspi_setup_opcode_ext(f_pdata, op, shift);
487 if (ret)
488 return ret;
593 int ret;
595 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB);
596 if (ret)
597 return ret;
643 ret = cqspi_exec_flash_cmd(cqspi, reg);
648 return ret;
658 int ret;
661 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB);
662 if (ret)
663 return ret;
705 int ret = 0;
733 ret = -ETIMEDOUT;
744 if (ret && bytes_to_read == 0) {
781 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
783 if (ret) {
784 dev_err(dev, "Indirect read completion error (%i)\n", ret);
803 return ret;
833 int ret = 0;
841 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA);
842 if (ret)
843 return ret;
898 ret = -ETIMEDOUT;
918 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id,
920 if (ret)
921 return ret;
927 ret = cqspi_indirect_read_execute(f_pdata, buf, addr,
929 if (ret)
930 return ret;
951 return ret;
958 int ret;
963 ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB);
964 if (ret)
965 return ret;
1019 int ret;
1071 ret = -ETIMEDOUT;
1082 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
1084 if (ret) {
1085 dev_err(dev, "Indirect write completion error (%i)\n", ret);
1106 return ret;
1263 int ret;
1265 ret = cqspi_write_setup(f_pdata, op);
1266 if (ret)
1267 return ret;
1300 int ret = 0;
1321 ret = -EIO;
1330 ret = dma_submit_error(cookie);
1331 if (ret) {
1333 ret = -EIO;
1342 ret = -ETIMEDOUT;
1349 return ret;
1362 int ret;
1366 ret = cqspi_read_setup(f_pdata, op);
1367 if (ret)
1368 return ret;
1409 int ret;
1411 ret = cqspi_mem_process(mem, op);
1412 if (ret)
1413 dev_err(&mem->spi->dev, "operation failed with %d\n", ret);
1415 return ret;
1576 int ret = PTR_ERR(cqspi->rx_chan);
1579 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1612 int ret;
1616 ret = of_property_read_u32(np, "reg", &cs);
1617 if (ret) {
1620 return ret;
1633 ret = cqspi_of_get_flash_pdata(pdev, f_pdata, np);
1634 if (ret) {
1636 return ret;
1650 int ret = 0;
1652 ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(qspiclk), qspiclk);
1653 if (ret) {
1655 return ret;
1661 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]);
1662 if (ret) {
1664 return ret;
1667 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]);
1668 if (ret) {
1680 return ret;
1696 int ret;
1717 ret = cqspi_of_get_pdata(cqspi);
1718 if (ret) {
1727 ret = PTR_ERR(cqspi->clk);
1728 return ret;
1735 ret = PTR_ERR(cqspi->iobase);
1736 return ret;
1743 ret = PTR_ERR(cqspi->ahb_base);
1744 return ret;
1757 ret = pm_runtime_resume_and_get(dev);
1758 if (ret < 0)
1761 ret = clk_prepare_enable(cqspi->clk);
1762 if (ret) {
1770 ret = PTR_ERR(rstc);
1777 ret = PTR_ERR(rstc_ocp);
1785 ret = PTR_ERR(rstc_ref);
1826 ret = cqspi_jh7110_clk_init(pdev, cqspi);
1827 if (ret)
1833 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1834 if (ret)
1839 ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
1841 if (ret) {
1853 ret = cqspi_setup_flash(cqspi);
1854 if (ret) {
1855 dev_err(dev, "failed to setup flash parameters %d\n", ret);
1860 ret = cqspi_request_mmap_dma(cqspi);
1861 if (ret == -EPROBE_DEFER)
1865 ret = spi_register_controller(host);
1866 if (ret) {
1867 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret);
1882 return ret;
1907 int ret;
1909 ret = spi_controller_suspend(cqspi->host);
1914 return ret;