Lines Matching refs:cqspi
58 struct cqspi_st *cqspi;
110 u32 (*get_dma_status)(struct cqspi_st *cqspi);
112 struct cqspi_st *cqspi);
302 static bool cqspi_is_idle(struct cqspi_st *cqspi)
304 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
309 static u32 cqspi_get_rd_sram_level(struct cqspi_st *cqspi)
311 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL);
317 static u32 cqspi_get_versal_dma_status(struct cqspi_st *cqspi)
321 dma_status = readl(cqspi->iobase +
323 writel(dma_status, cqspi->iobase +
331 struct cqspi_st *cqspi = dev;
333 struct device *device = &cqspi->pdev->dev;
339 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS);
342 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS);
344 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) {
345 if (ddata->get_dma_status(cqspi)) {
346 complete(&cqspi->transfer_complete);
351 else if (!cqspi->slow_sram)
357 complete(&cqspi->transfer_complete);
387 static int cqspi_wait_idle(struct cqspi_st *cqspi)
400 if (cqspi_is_idle(cqspi))
410 dev_err(&cqspi->pdev->dev,
420 static int cqspi_exec_flash_cmd(struct cqspi_st *cqspi, unsigned int reg)
422 void __iomem *reg_base = cqspi->iobase;
435 dev_err(&cqspi->pdev->dev,
441 return cqspi_wait_idle(cqspi);
448 struct cqspi_st *cqspi = f_pdata->cqspi;
449 void __iomem *reg_base = cqspi->iobase;
470 struct cqspi_st *cqspi = f_pdata->cqspi;
471 void __iomem *reg_base = cqspi->iobase;
496 return cqspi_wait_idle(cqspi);
502 struct cqspi_st *cqspi = f_pdata->cqspi;
503 void __iomem *reg_base = cqspi->iobase;
518 dev_err(&cqspi->pdev->dev,
558 status = cqspi_exec_flash_cmd(cqspi, reg);
585 struct cqspi_st *cqspi = f_pdata->cqspi;
586 void __iomem *reg_base = cqspi->iobase;
600 dev_err(&cqspi->pdev->dev,
643 ret = cqspi_exec_flash_cmd(cqspi, reg);
654 struct cqspi_st *cqspi = f_pdata->cqspi;
655 void __iomem *reg_base = cqspi->iobase;
697 struct cqspi_st *cqspi = f_pdata->cqspi;
698 struct device *dev = &cqspi->pdev->dev;
699 void __iomem *reg_base = cqspi->iobase;
700 void __iomem *ahb_base = cqspi->ahb_base;
721 if (!cqspi->slow_sram)
726 reinit_completion(&cqspi->transfer_complete);
731 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
739 if (cqspi->slow_sram)
742 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
752 bytes_to_read *= cqspi->fifo_width;
770 bytes_to_read = cqspi_get_rd_sram_level(cqspi);
774 reinit_completion(&cqspi->transfer_complete);
775 if (cqspi->slow_sram)
806 static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable)
808 void __iomem *reg_base = cqspi->iobase;
825 struct cqspi_st *cqspi = f_pdata->cqspi;
826 struct device *dev = &cqspi->pdev->dev;
827 void __iomem *reg_base = cqspi->iobase;
841 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA);
845 cqspi_controller_enable(cqspi, 0);
847 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
849 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
851 cqspi_controller_enable(cqspi, 1);
881 writel(cqspi->trigger_address, reg_base +
894 reinit_completion(&cqspi->transfer_complete);
896 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
903 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
907 cqspi->iobase + CQSPI_REG_INDIRECTRD);
910 cqspi_controller_enable(cqspi, 0);
912 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
914 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
916 cqspi_controller_enable(cqspi, 1);
918 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id,
945 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
947 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
949 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR);
959 struct cqspi_st *cqspi = f_pdata->cqspi;
960 void __iomem *reg_base = cqspi->iobase;
991 if (cqspi->wr_completion) {
1000 cqspi->use_direct_mode_wr = false;
1014 struct cqspi_st *cqspi = f_pdata->cqspi;
1015 struct device *dev = &cqspi->pdev->dev;
1016 void __iomem *reg_base = cqspi->iobase;
1029 reinit_completion(&cqspi->transfer_complete);
1039 if (cqspi->wr_delay)
1040 ndelay(cqspi->wr_delay);
1046 if (cqspi->apb_ahb_hazard)
1057 iowrite32_rep(cqspi->ahb_base, txbuf, write_words);
1064 iowrite32(temp, cqspi->ahb_base);
1068 if (!wait_for_completion_timeout(&cqspi->transfer_complete,
1078 reinit_completion(&cqspi->transfer_complete);
1095 cqspi_wait_idle(cqspi);
1111 struct cqspi_st *cqspi = f_pdata->cqspi;
1112 void __iomem *reg_base = cqspi->iobase;
1117 if (cqspi->is_decoded_cs) {
1151 struct cqspi_st *cqspi = f_pdata->cqspi;
1152 void __iomem *iobase = cqspi->iobase;
1153 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1159 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk);
1181 static void cqspi_config_baudrate_div(struct cqspi_st *cqspi)
1183 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz;
1184 void __iomem *reg_base = cqspi->iobase;
1188 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1;
1193 dev_warn(&cqspi->pdev->dev,
1195 cqspi->sclk, ref_clk_hz/((div+1)*2));
1204 static void cqspi_readdata_capture(struct cqspi_st *cqspi,
1208 void __iomem *reg_base = cqspi->iobase;
1230 struct cqspi_st *cqspi = f_pdata->cqspi;
1231 int switch_cs = (cqspi->current_cs != f_pdata->cs);
1232 int switch_ck = (cqspi->sclk != sclk);
1235 cqspi_controller_enable(cqspi, 0);
1239 cqspi->current_cs = f_pdata->cs;
1245 cqspi->sclk = sclk;
1246 cqspi_config_baudrate_div(cqspi);
1248 cqspi_readdata_capture(cqspi, !cqspi->rclk_en,
1253 cqspi_controller_enable(cqspi, 1);
1259 struct cqspi_st *cqspi = f_pdata->cqspi;
1277 if (!op->cmd.dtr && cqspi->use_direct_mode &&
1278 cqspi->use_direct_mode_wr && ((to + len) <= cqspi->ahb_size)) {
1279 memcpy_toio(cqspi->ahb_base + to, buf, len);
1280 return cqspi_wait_idle(cqspi);
1288 struct cqspi_st *cqspi = param;
1290 complete(&cqspi->rx_dma_complete);
1296 struct cqspi_st *cqspi = f_pdata->cqspi;
1297 struct device *dev = &cqspi->pdev->dev;
1299 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from;
1306 if (!cqspi->rx_chan || !virt_addr_valid(buf)) {
1307 memcpy_fromio(buf, cqspi->ahb_base + from, len);
1311 ddev = cqspi->rx_chan->device->dev;
1317 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src,
1326 tx->callback_param = cqspi;
1328 reinit_completion(&cqspi->rx_dma_complete);
1337 dma_async_issue_pending(cqspi->rx_chan);
1338 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete,
1340 dmaengine_terminate_sync(cqspi->rx_chan);
1355 struct cqspi_st *cqspi = f_pdata->cqspi;
1356 struct device *dev = &cqspi->pdev->dev;
1370 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size))
1373 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma &&
1382 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
1385 f_pdata = &cqspi->f_pdata[spi_get_chipselect(mem->spi, 0)];
1488 static int cqspi_of_get_pdata(struct cqspi_st *cqspi)
1490 struct device *dev = &cqspi->pdev->dev;
1494 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs");
1496 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) {
1501 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) {
1507 &cqspi->trigger_address)) {
1512 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect))
1513 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT;
1515 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en");
1519 cqspi->pd_dev_id = id[1];
1524 static void cqspi_controller_init(struct cqspi_st *cqspi)
1528 cqspi_controller_enable(cqspi, 0);
1531 writel(0, cqspi->iobase + CQSPI_REG_REMAP);
1534 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK);
1537 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION);
1540 writel(cqspi->trigger_address,
1541 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER);
1544 writel(cqspi->fifo_depth * cqspi->fifo_width / 2,
1545 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK);
1547 writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
1548 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
1551 if (!cqspi->use_direct_mode) {
1552 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1554 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1558 if (cqspi->use_dma_read) {
1559 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
1561 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
1564 cqspi_controller_enable(cqspi, 1);
1567 static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
1574 cqspi->rx_chan = dma_request_chan_by_mask(&mask);
1575 if (IS_ERR(cqspi->rx_chan)) {
1576 int ret = PTR_ERR(cqspi->rx_chan);
1578 cqspi->rx_chan = NULL;
1579 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n");
1581 init_completion(&cqspi->rx_dma_complete);
1588 struct cqspi_st *cqspi = spi_controller_get_devdata(mem->spi->controller);
1589 struct device *dev = &cqspi->pdev->dev;
1605 static int cqspi_setup_flash(struct cqspi_st *cqspi)
1607 struct platform_device *pdev = cqspi->pdev;
1629 f_pdata = &cqspi->f_pdata[cs];
1630 f_pdata->cqspi = cqspi;
1643 static int cqspi_jh7110_clk_init(struct platform_device *pdev, struct cqspi_st *cqspi)
1658 cqspi->clks[CLK_QSPI_APB] = qspiclk[0].clk;
1659 cqspi->clks[CLK_QSPI_AHB] = qspiclk[1].clk;
1661 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_APB]);
1667 ret = clk_prepare_enable(cqspi->clks[CLK_QSPI_AHB]);
1673 cqspi->is_jh7110 = true;
1678 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]);
1683 static void cqspi_jh7110_disable_clk(struct platform_device *pdev, struct cqspi_st *cqspi)
1685 clk_disable_unprepare(cqspi->clks[CLK_QSPI_AHB]);
1686 clk_disable_unprepare(cqspi->clks[CLK_QSPI_APB]);
1695 struct cqspi_st *cqspi;
1699 host = devm_spi_alloc_host(&pdev->dev, sizeof(*cqspi));
1709 cqspi = spi_controller_get_devdata(host);
1711 cqspi->pdev = pdev;
1712 cqspi->host = host;
1713 cqspi->is_jh7110 = false;
1714 platform_set_drvdata(pdev, cqspi);
1717 ret = cqspi_of_get_pdata(cqspi);
1724 cqspi->clk = devm_clk_get(dev, NULL);
1725 if (IS_ERR(cqspi->clk)) {
1727 ret = PTR_ERR(cqspi->clk);
1732 cqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
1733 if (IS_ERR(cqspi->iobase)) {
1735 ret = PTR_ERR(cqspi->iobase);
1740 cqspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res_ahb);
1741 if (IS_ERR(cqspi->ahb_base)) {
1743 ret = PTR_ERR(cqspi->ahb_base);
1746 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start;
1747 cqspi->ahb_size = resource_size(res_ahb);
1749 init_completion(&cqspi->transfer_complete);
1761 ret = clk_prepare_enable(cqspi->clk);
1799 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
1800 host->max_speed_hz = cqspi->master_ref_clk_hz;
1803 cqspi->wr_completion = true;
1808 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC,
1809 cqspi->master_ref_clk_hz);
1813 cqspi->use_direct_mode = true;
1814 cqspi->use_direct_mode_wr = true;
1817 cqspi->use_dma_read = true;
1819 cqspi->wr_completion = false;
1821 cqspi->slow_sram = true;
1823 cqspi->apb_ahb_hazard = true;
1826 ret = cqspi_jh7110_clk_init(pdev, cqspi);
1840 pdev->name, cqspi);
1846 cqspi_wait_idle(cqspi);
1847 cqspi_controller_init(cqspi);
1848 cqspi->current_cs = -1;
1849 cqspi->sclk = 0;
1851 host->num_chipselect = cqspi->num_chipselect;
1853 ret = cqspi_setup_flash(cqspi);
1859 if (cqspi->use_direct_mode) {
1860 ret = cqspi_request_mmap_dma(cqspi);
1873 cqspi_controller_enable(cqspi, 0);
1875 if (cqspi->is_jh7110)
1876 cqspi_jh7110_disable_clk(pdev, cqspi);
1877 clk_disable_unprepare(cqspi->clk);
1887 struct cqspi_st *cqspi = platform_get_drvdata(pdev);
1889 spi_unregister_controller(cqspi->host);
1890 cqspi_controller_enable(cqspi, 0);
1892 if (cqspi->rx_chan)
1893 dma_release_channel(cqspi->rx_chan);
1895 clk_disable_unprepare(cqspi->clk);
1897 if (cqspi->is_jh7110)
1898 cqspi_jh7110_disable_clk(pdev, cqspi);
1906 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1909 ret = spi_controller_suspend(cqspi->host);
1910 cqspi_controller_enable(cqspi, 0);
1912 clk_disable_unprepare(cqspi->clk);
1919 struct cqspi_st *cqspi = dev_get_drvdata(dev);
1921 clk_prepare_enable(cqspi->clk);
1922 cqspi_wait_idle(cqspi);
1923 cqspi_controller_init(cqspi);
1925 cqspi->current_cs = -1;
1926 cqspi->sclk = 0;
1928 return spi_controller_resume(cqspi->host);