Lines Matching defs:reg_base
422 void __iomem *reg_base = cqspi->iobase;
426 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
429 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
432 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_CMDCTRL,
449 void __iomem *reg_base = cqspi->iobase;
459 reg = readl(reg_base + CQSPI_REG_OP_EXT_LOWER);
462 writel(reg, reg_base + CQSPI_REG_OP_EXT_LOWER);
471 void __iomem *reg_base = cqspi->iobase;
475 reg = readl(reg_base + CQSPI_REG_CONFIG);
494 writel(reg, reg_base + CQSPI_REG_CONFIG);
503 void __iomem *reg_base = cqspi->iobase;
532 writel(rdreg, reg_base + CQSPI_REG_RD_INSTR);
555 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
562 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
570 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
577 writel(0, reg_base + CQSPI_REG_CMDCTRL);
586 void __iomem *reg_base = cqspi->iobase;
607 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
622 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS);
633 writel(data, reg_base + CQSPI_REG_CMDWRITEDATALOWER);
639 writel(data, reg_base + CQSPI_REG_CMDWRITEDATAUPPER);
646 writel(0, reg_base + CQSPI_REG_CMDCTRL);
655 void __iomem *reg_base = cqspi->iobase;
683 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
686 reg = readl(reg_base + CQSPI_REG_SIZE);
689 writel(reg, reg_base + CQSPI_REG_SIZE);
699 void __iomem *reg_base = cqspi->iobase;
707 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
708 writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
711 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
722 writel(CQSPI_IRQ_MASK_RD, reg_base + CQSPI_REG_IRQMASK);
724 writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
728 reg_base + CQSPI_REG_INDIRECTRD);
740 writel(0x0, reg_base + CQSPI_REG_IRQMASK);
776 writel(CQSPI_REG_IRQ_WATERMARK, reg_base + CQSPI_REG_IRQMASK);
781 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
789 writel(0, reg_base + CQSPI_REG_IRQMASK);
792 writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
798 writel(0, reg_base + CQSPI_REG_IRQMASK);
802 reg_base + CQSPI_REG_INDIRECTRD);
808 void __iomem *reg_base = cqspi->iobase;
811 reg = readl(reg_base + CQSPI_REG_CONFIG);
818 writel(reg, reg_base + CQSPI_REG_CONFIG);
827 void __iomem *reg_base = cqspi->iobase;
859 writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
860 writel(bytes_to_dma, reg_base + CQSPI_REG_INDIRECTRDBYTES);
862 reg_base + CQSPI_REG_INDTRIG_ADDRRANGE);
865 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
869 reg_base + CQSPI_REG_VERSAL_DMA_DST_I_EN);
872 writel(CQSPI_REG_VERSAL_DMA_VAL, reg_base + CQSPI_REG_DMA);
876 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR);
878 reg_base + CQSPI_REG_VERSAL_DMA_DST_ADDR_MSB);
881 writel(cqspi->trigger_address, reg_base +
885 writel(bytes_to_dma, reg_base + CQSPI_REG_VERSAL_DMA_DST_SIZE);
889 reg_base + CQSPI_REG_VERSAL_DMA_DST_CTRL);
892 reg_base + CQSPI_REG_INDIRECTRD);
937 writel(0x0, reg_base + CQSPI_REG_VERSAL_DMA_DST_I_DIS);
941 reg_base + CQSPI_REG_INDIRECTRD);
960 void __iomem *reg_base = cqspi->iobase;
976 writel(reg, reg_base + CQSPI_REG_WR_INSTR);
978 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
992 reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
994 writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
1003 reg = readl(reg_base + CQSPI_REG_SIZE);
1006 writel(reg, reg_base + CQSPI_REG_SIZE);
1016 void __iomem *reg_base = cqspi->iobase;
1021 writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
1022 writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
1025 writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
1027 writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
1031 reg_base + CQSPI_REG_INDIRECTWR);
1047 readl(reg_base + CQSPI_REG_INDIRECTWR);
1082 ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTWR,
1090 writel(0, reg_base + CQSPI_REG_IRQMASK);
1093 writel(CQSPI_REG_INDIRECTWR_DONE_MASK, reg_base + CQSPI_REG_INDIRECTWR);
1101 writel(0, reg_base + CQSPI_REG_IRQMASK);
1105 reg_base + CQSPI_REG_INDIRECTWR);
1112 void __iomem *reg_base = cqspi->iobase;
1116 reg = readl(reg_base + CQSPI_REG_CONFIG);
1135 writel(reg, reg_base + CQSPI_REG_CONFIG);
1184 void __iomem *reg_base = cqspi->iobase;
1198 reg = readl(reg_base + CQSPI_REG_CONFIG);
1201 writel(reg, reg_base + CQSPI_REG_CONFIG);
1208 void __iomem *reg_base = cqspi->iobase;
1211 reg = readl(reg_base + CQSPI_REG_READCAPTURE);
1224 writel(reg, reg_base + CQSPI_REG_READCAPTURE);